From d2f1c569a7696f4cfeb0d236ae05f93d6d7ef77e Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Tue, 21 Nov 2023 15:23:05 +0100 Subject: [PATCH] FPGA: Modify FPGA register map (move action configuration to offset 0x200) --- common/Definitions.h | 2 +- fpga/README.md | 19 ++++++++++--------- fpga/hdl/action_config.v | 22 +++++++++++----------- fpga/pcie_driver/jfjoch_drv.h | 18 +++++++++--------- 4 files changed, 31 insertions(+), 30 deletions(-) diff --git a/common/Definitions.h b/common/Definitions.h index b6c6a317..29b9d649 100644 --- a/common/Definitions.h +++ b/common/Definitions.h @@ -48,7 +48,7 @@ // For FPGA #define ACTION_TYPE 0x52324158 -#define RELEASE_LEVEL 0x0045 +#define RELEASE_LEVEL 0x0046 #define MODE_CONV 0x0001L #define MODE_BITSHUFFLE_FPGA 0x0002L diff --git a/fpga/README.md b/fpga/README.md index b69ed509..c6c8adac 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -141,17 +141,18 @@ FPGA setup can be done via 32-bit registers: | 0x010058 | 64 | Valid UDP packets | R | cleared on reset | | 0x010060 | 64 | Valid detector packets processed by the card | R | cleared on reset | | 0x010066 | 64 | Packets flagged as errors by CMAC | R | cleared on reset | -| 0x010080 | 64 | MAC address of FPGA card | R/W | network byte order | -| 0x010088 | 32 | IPv4 address of FPGA card | R/W | network byte order | -| 0x01008C | 32 | Number of detector modules | R/W | | -| 0x010090 | 32 | Data collection mode | R/W | | -| | | Bit 0 - Conversion to photons | | | -| | | Bit 16:31 - Data collection ID (carried with completions) | | | -| 0x010094 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | | -| 0x010098 | 32 | Number of frames expected in the data collection (defines termination condition) | R/W | | -| 0x01009C | 32 | Number of storage cells | R/W | | | 0x010100 | 32 | Spot finder photon count threshold | R/W | | | 0x010104 | 32 | Spot finder signal-to-noise ratio threshold (in fixed-point: 6 int. + 4 frac. bit format) | R/W | | +| 0x010200 | 64 | MAC address of FPGA card | R/W | network byte order | +| 0x010208 | 32 | IPv4 address of FPGA card | R/W | network byte order | +| 0x01020C | 32 | Number of detector modules | R/W | | +| 0x010210 | 32 | Data collection mode | R/W | | +| | | Bit 0 - Conversion to photons | | | +| | | Bit 16:31 - Data collection ID (carried with completions) | | | +| 0x010214 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | | +| 0x010218 | 32 | Number of frames expected in the data collection (defines termination condition) | R/W | | +| 0x01021C | 32 | Number of storage cells | R/W | | +| 0x010220 | 32 | Summation on card (minus one: 0 => summation of 1, 1 => summation of 2, etc.) | R/W | | | 0x020000 - 0x02FFFF | | CMAC 100G | | See Xilinx PG203 for register map | | 0x030000 - 0x03FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map | | 0x040000 - 0x04FFFF | | QuadSPI flash | | See Xilinx PG153 for register map | diff --git a/fpga/hdl/action_config.v b/fpga/hdl/action_config.v index 88d2a502..03e19e05 100644 --- a/fpga/hdl/action_config.v +++ b/fpga/hdl/action_config.v @@ -38,20 +38,20 @@ `define ADDR_PACKETS_ERR_LEN 16'h0068 `define ADDR_PACKETS_ERR_ETH 16'h006C -`define ADDR_MAC_ADDR_LO 16'h0080 -`define ADDR_MAC_ADDR_HI 16'h0084 -`define ADDR_IPV4_ADDR 16'h0088 -`define ADDR_NMODULES 16'h008C - -`define ADDR_DATA_COL_MODE 16'h0090 -`define ADDR_ONE_OVER_ENERGY 16'h0094 -`define ADDR_NFRAMES 16'h0098 -`define ADDR_NSTORAGE_CELLS 16'h009C -`define ADDR_NSUMMATION 16'h00A0 - `define ADDR_SPOT_FINDER_CNT_THR 16'h0100 `define ADDR_SPOT_FINDER_SNR_THR 16'h0104 +`define ADDR_MAC_ADDR_LO 16'h0200 +`define ADDR_MAC_ADDR_HI 16'h0204 +`define ADDR_IPV4_ADDR 16'h0208 +`define ADDR_NMODULES 16'h020C + +`define ADDR_DATA_COL_MODE 16'h0210 +`define ADDR_ONE_OVER_ENERGY 16'h0214 +`define ADDR_NFRAMES 16'h0218 +`define ADDR_NSTORAGE_CELLS 16'h021C + +`define ADDR_NSUMMATION 16'h0220 module action_config #(parameter C_S_AXI_ADDR_WIDTH = 16, diff --git a/fpga/pcie_driver/jfjoch_drv.h b/fpga/pcie_driver/jfjoch_drv.h index 368b0db2..807c893c 100644 --- a/fpga/pcie_driver/jfjoch_drv.h +++ b/fpga/pcie_driver/jfjoch_drv.h @@ -43,7 +43,7 @@ #define PCIE_OFFSET (0x090000) #define FRAME_GEN_OFFSET (0x080000) - +// Action config #define ADDR_CTRL_REGISTER 0x0000 #define ADDR_GIT_SHA1 0x000C #define ADDR_ACTION_TYPE 0x0010 @@ -70,14 +70,14 @@ #define ADDR_PACKETS_ERR_LEN 0x0068 #define ADDR_PACKETS_ERR_ETH 0x006C -#define ADDR_MAC_ADDR_LO 0x0080 -#define ADDR_MAC_ADDR_HI 0x0084 -#define ADDR_IPV4_ADDR 0x0088 -#define ADDR_NMODULES 0x008C -#define ADDR_DATA_COL_MODE 0x0090 -#define ADDR_ONE_OVER_ENERGY 0x0094 -#define ADDR_NFRAMES 0x0098 -#define ADDR_NSTORAGE_CELLS 0x009C +#define ADDR_MAC_ADDR_LO 0x0200 +#define ADDR_MAC_ADDR_HI 0x0204 +#define ADDR_IPV4_ADDR 0x0208 +#define ADDR_NMODULES 0x020C +#define ADDR_DATA_COL_MODE 0x0210 +#define ADDR_ONE_OVER_ENERGY 0x0214 +#define ADDR_NFRAMES 0x0218 +#define ADDR_NSTORAGE_CELLS 0x021C #define ADDR_SPOT_FINDER_THRESHOLD 0x0100 #define ADDR_SPOT_FINDER_SNR 0x0104