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FPGA: Increase max summation to 256

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This commit is contained in:
leonarski_f
2023-11-16 21:32:37 +01:00
parent 4bb306d071
commit 1e6f64b4da
6 changed files with 10 additions and 11 deletions
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3
common/Definitions.h
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@@ -21,7 +21,6 @@
#define MIN_FRAME_TIME_HALF_SPEED_IN_US 1000
#define MIN_FRAME_TIME_FULL_SPEED_IN_US 470
#define MAX_FRAME_TIME 2000
#define MAX_SUMMATION 5000
#define MIN_STORAGE_CELL_DELAY_IN_NS 2100
#define READOUT_TIME_IN_US 20
@@ -134,7 +133,7 @@
#define FPGA_INTEGRATION_BIN_COUNT 1024
#define MAX_MODULES_FPGA 32
#define MAX_FPGA_SUMMATION 128
#define MAX_FPGA_SUMMATION 256
#define ADU_HISTO_BIN_WIDTH 32
#define ADU_HISTO_BIN_COUNT (65536/ ADU_HISTO_BIN_WIDTH)

4
fpga/hdl/action_config.v
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@@ -91,7 +91,7 @@ module action_config
output reg [31:0] nframes ,
output reg [4:0] nmodules ,
output reg [3:0] nstorage_cells ,
output reg [6:0] nsummation ,
output reg [7:0] nsummation ,
output wire [31:0] hbm_size_bytes ,
output reg [15:0] spot_finder_count_threshold,
output reg [7:0] spot_finder_snr_threshold,
@@ -529,7 +529,7 @@ always @(posedge clk) begin
nsummation <= 0;
else if (reg_data_collection_idle) begin
if (w_hs && waddr == `ADDR_NSUMMATION)
nsummation <= (s_axi_WDATA[6:0] & wmask[6:0]) | (nsummation & !wmask[6:0]);
nsummation <= (s_axi_WDATA[7:0] & wmask[7:0]) | (nsummation & !wmask[7:0]);
end
end

2
fpga/hls/data_collection_fsm.cpp
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@@ -15,7 +15,7 @@ void data_collection_fsm(AXI_STREAM &eth_in,
ap_uint<32> nframes,
ap_uint<5> nmodules,
ap_uint<4> nstorage_cells,
ap_uint<7> nsummation) {
ap_uint<8> nsummation) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE axis register both port=eth_in

2
fpga/hls/frame_summation.cpp
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@@ -36,7 +36,7 @@ void frame_summation(STREAM_576 &data_in, STREAM_768 &data_out,
packet_768_t packet_out;
data_in >> packet_in;
ap_uint<7> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..127
ap_uint<8> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..255
data_out << packet_768_t{.data = packet_in.data, .user = 0, .last = 0};
data_in >> packet_in;

6
fpga/hls/frame_summation_reorder_compl.cpp
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@@ -13,12 +13,12 @@ void frame_summation_reorder_compl(STREAM_512 &data_in,
packet_512_t packet_in;
data_in >> packet_in;
ap_uint<7> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..127
ap_uint<8> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..255
data_out << packet_in;
axis_completion completions[MAX_FPGA_SUMMATION * MAX_MODULES_FPGA];
ap_uint<MAX_FPGA_SUMMATION> completion_mask[MAX_MODULES_FPGA];
ap_uint<5> completion_count[MAX_MODULES_FPGA];
ap_uint<9> completion_count[MAX_MODULES_FPGA]; // must represent 256
ap_uint<64> curr_frame_number_prefix[MAX_MODULES_FPGA];
@@ -33,7 +33,7 @@ void frame_summation_reorder_compl(STREAM_512 &data_in,
while (!c.last) {
#pragma HLS PIPELINE II=16
ap_uint<64> frame_number_prefix = c.frame_number / (sum + 1);
ap_uint<5> frame_number_loc = c.frame_number % (sum + 1);
ap_uint<8> frame_number_loc = c.frame_number % (sum + 1); // 0..255
ap_uint<7> module = c.module;
if (frame_number_prefix > curr_frame_number_prefix[module]) {
for (int i = 0; i <= sum; i++) {

4
fpga/hls/hls_jfjoch.h
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@@ -58,7 +58,7 @@ typedef hls::stream<packet_768_t> STREAM_768;
#define ACT_REG_NFRAMES(x) ((x)(95 , 64)) // 32 bit
#define ACT_REG_NMODULES(x) ((x)(132, 128)) // 5 bit (0..31)
#define ACT_REG_NSTORAGE_CELLS(x) ((x)(148, 144)) // 5 bit
#define ACT_REG_NSUMMATION(x) ((x)(166, 160)) // 7 bit (0..127)
#define ACT_REG_NSUMMATION(x) ((x)(167, 160)) // 7 bit (0..255)
struct axis_datamover_ctrl {
ap_uint<40+64> data;
@@ -279,7 +279,7 @@ void data_collection_fsm(AXI_STREAM &eth_in,
ap_uint<32> nframes,
ap_uint<5> nmodules,
ap_uint<4> nstorage_cells,
ap_uint<7> nsummation);
ap_uint<8> nsummation);
void host_writer(STREAM_512 &data_in,
hls::stream<ap_uint<512>> &adu_histo_in,