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Author SHA1 Message Date
leonarski_f 2ed91c1849 FPGA: transfer for image and processing results are separate DMA transactions 2023-10-28 16:47:06 +02:00
leonarski_f 961c17c4d0 FPGA: data analysis is done based on 24-bit numbers - allowing frame summation 2023-10-28 16:35:33 +02:00
leonarski_f fbc4f79a40 FPGA: Frame_summation operates internally on 24-bit integers 2023-10-28 06:22:06 +02:00
leonarski_f 4fbd747341 FPGA: Remove multipixel from the pipeline 2023-10-27 20:47:44 +02:00
leonarski_f 4978149fdd FPGA: Add register slice in the data pipeline 2023-10-27 19:43:40 +02:00
leonarski_f c896ec5659 FPGA: Remove bitshuffle from the pipeline 2023-10-27 19:41:02 +02:00
leonarski_f f46a8e47a0 FPGA: Use AggressiveExplore for routing 2023-10-27 19:12:27 +02:00
leonarski_f 817d541fb0 HLS: save_to_hbm.cpp send frames in proper order 2023-10-27 16:02:23 +02:00
leonarski_f 08c2427fc7 FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign 2023-10-27 15:42:24 +02:00
leonarski_f e06086e956 HLSSimulatedDevice: Change order integration -> frame_summation -> spot finding 2023-10-27 15:41:09 +02:00
leonarski_f b08071887b HLSSimulatedDevice: Add frame_summation 2023-10-27 15:36:19 +02:00
leonarski_f 700d5b25af HLSSimulatedDevice: Add frame_summation_reoder_compl 2023-10-27 15:33:29 +02:00
leonarski_f 3b802effa8 HLSSimulatedDevice: Remove module_upside_down 2023-10-27 15:28:49 +02:00
leonarski_f 7973c2ca81 HLS: Minor fixes to adu_histo.cpp 2023-10-27 15:27:36 +02:00
leonarski_f 4fbac629d6 HLS: Use U55C part number for proper usage statistics 2023-10-27 13:54:35 +02:00
leonarski_f cf69aef472 FPGA: Add extra register slices for upside_down 2023-10-26 22:36:08 +02:00
leonarski_f 2268486824 HLS: Added frame_summation core 2023-10-26 22:31:09 +02:00
leonarski_f 4011c4541d HLS: frames inside HLS logic are counted from 0, even if JUNGFRAU counts them from 1 2023-10-26 19:42:15 +02:00
leonarski_f 473bf17ae7 HLS: axis_completion has extra parameter (ignore) that makes the frame ignored by load_from_hbm, but HBM handle is still recovered 2023-10-26 18:14:35 +02:00
leonarski_f efac89f89e FPGAIntegrationTest: Add invert and bitshuffle tests 2023-10-25 22:37:25 +02:00
leonarski_f 7df76a5c76 FPGAAcquisitionDevice: add option to customize execution flags 2023-10-25 22:28:13 +02:00
leonarski_f 4e60bb2f9e FPGA: Add option to invert modules upside down 2023-10-25 22:20:45 +02:00
leonarski_f 439d6fa12a FPGA: Spot finder won't use multipixels for mean/variance calculation 2023-10-25 18:18:29 +02:00
leonarski_f 6bcf54f603 FPGA: Add bitshuffle to the design (warning! no test for full integration!) 2023-10-25 11:07:21 +02:00
leonarski_f a611d3f08b FPGA: Adapt host writer to multipixel core. (TODO -> multipixels should be masked for rad. int. and spot finding) 2023-10-24 19:11:23 +02:00
leonarski_f d408b3ed2a FPGA: Integrate add multipixel into the design 2023-10-24 18:58:59 +02:00
leonarski_f b33e996569 FPGA: Add multipixel - add test. 2023-10-24 18:05:59 +02:00
leonarski_f c37a9fa768 FPGA: Add multipixel - handle division by 2 and 4 for multipixels. 2023-10-24 18:05:48 +02:00
leonarski_f e195432aea RawToConvertedGeometry: Separate core functions that require minimum headers 2023-10-24 17:54:14 +02:00
leonarski_f e1a6830c50 FPGA: Add multipixel (-> TODO calculate proper number) 2023-10-24 16:43:24 +02:00
leonarski_f 6d74732bf5 Merge branch 'fpga_hbm_cache' into 'main' 
Introduce HBM cache into the design

See merge request jungfraujoch/nextgendcu!7
 2023-10-22 16:11:21 +02:00
leonarski_f 61f4adf743 Merge branch 'main' into 'fpga_hbm_cache' 
# Conflicts:
#   etc/broker.json
#   python/jfjoch_pb2.py
#   receiver/FPGAAcquisitionDevice.cpp
#   receiver/FPGAAcquisitionDevice.h
#   receiver/jfjoch_action_test.cpp
#   tests/FPGAIntegrationTest.cpp
#   tests/JFJochReceiverIntegrationTest.cpp
 2023-10-22 13:55:41 +00:00
leonarski_f ea0fccecc9 JFConversionGPU: Remove 2023-10-22 14:39:03 +02:00
leonarski_f c1469d1e46 JFJochReceiver: Skip frames if acquisition finished and frames stopped earlier on the first acquisition device 2023-10-22 14:36:53 +02:00
leonarski_f bc43921004 JFJochReceiver: Remove local conversion (not useful -> simplify) 2023-10-22 13:45:47 +02:00
leonarski_f fe5b955289 GPUImageAnalysis: Spot finder again produces 1-bit result (similar to FPGA) reduced on CPU + mask is not applied on GPU 2023-10-22 13:42:09 +02:00
leonarski_f 566ff52bfc JFJochReceiver: Single preview, that can be switched to present all or indexed only results 2023-10-22 12:41:59 +02:00
leonarski_f af27854440 Frontend: Add ADU histogram plot 2023-10-21 23:08:17 +02:00
leonarski_f ee363a8356 JFJochReceiver: Given firmware now masks uncollected parts of the image, receiver will accept partial modules (but not for pedestal!) 2023-10-21 23:01:17 +02:00
leonarski_f 624c928c84 JFJochReceiver: ADU histogram saved on per module basis at the end of the measurement (but not on per image basis) 2023-10-21 22:31:43 +02:00
leonarski_f 99741ae5c5 ADU histogram: Save 2023-10-21 19:51:25 +02:00
leonarski_f 53f4f4acf9 RadialIntegration: Calculate only on FPGA 2023-10-21 19:15:42 +02:00
leonarski_f dd4988486c RadialIntegrationMapping: No mask 2023-10-21 17:20:12 +02:00
leonarski_f b4ab3087f1 RadialIntegrationProfile: Extra routines to handle GPU/CPU/FPGA workflows in more versatile way 2023-10-21 17:14:17 +02:00
leonarski_f a7706546b7 RadialIntegration: Remove pixel split 2023-10-21 16:18:41 +02:00
leonarski_f 19644a1f5f FPGA: Trigger synthesis 2023-10-21 16:12:51 +02:00
leonarski_f c86bc4591c AcquisitionDevice: Remove automatic setup of radial integration 2023-10-21 16:08:49 +02:00
leonarski_f 4ede0f1f15 FPGA: rename axis_256_to_512.cpp file 2023-10-21 15:38:40 +02:00
leonarski_f 3b65e6bf88 FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5) 2023-10-21 15:37:46 +02:00
leonarski_f d91eb6bdd5 FPGAIntegrationTest: Use multiple modules 2023-10-21 11:08:07 +02:00