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0b480f762c
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v1.0.0-rc.93
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2025-10-23 15:48:46 +02:00 |
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061152279c
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v1.0.0-rc.91
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2025-10-20 20:43:44 +02:00 |
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c67337cfe1
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v1.0.0-rc.72
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2025-09-08 20:28:59 +02:00 |
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b0607ab3ca
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v1.0.0-rc.34
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2025-04-14 11:52:06 +02:00 |
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a30707964d
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v.1.0.0-rc.32
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2025-03-24 12:16:33 +01:00 |
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ddf4c75645
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v1.0.0-rc.31
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2025-03-02 13:15:28 +01:00 |
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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40c1e3d49f
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version 1.0.0-rc.20
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2024-10-21 13:30:56 +02:00 |
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4ae0668f2f
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Fixes to 8x10g FPGA image and frontend
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2024-10-16 09:12:24 +02:00 |
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3be959f272
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version 1.0.0-rc.14
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2024-10-07 11:56:40 +02:00 |
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e812918e2e
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version 1.0.0-rc.13
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2024-10-05 13:14:49 +02:00 |
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3e5ed2e9f9
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1.0.0-rc.12 Minor fixes
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2024-07-08 19:58:27 +02:00 |
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6b5fddf2b7
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Version 1.0.0-rc.12
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2024-07-06 09:34:44 +02:00 |
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91fd44bff7
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Improve release/versioning of Jungfraujoch repository
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2024-05-15 11:29:01 +02:00 |
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5312f3ea6a
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Improvements in building Jungfraujoch
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2024-05-06 21:28:55 +02:00 |
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c6d2b5eedf
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File writer and spot finding improvements
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2024-04-08 11:18:50 +02:00 |
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59aacf516d
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Updates March 2023
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2024-03-14 20:26:03 +01:00 |
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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6e85a30930
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FPGA: Change FIFO size to improve placing
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2024-01-28 20:11:39 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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07fd769102
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Remove AN/LT capability
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2023-12-18 12:33:31 +01:00 |
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d66b6b949d
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Fix spot finding + fix FPGA network LEDs behavior
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2023-12-16 09:20:46 +01:00 |
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d82bd13917
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Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
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2023-12-14 22:39:17 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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1d3d8d081e
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FPGA: add power report after routing
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2023-11-28 21:30:40 +01:00 |
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657cf802eb
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FPGA: frame_summation_reorder_compl doesn't need ap_start
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2023-11-23 16:39:48 +01:00 |
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a7c2849a84
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FPGA: measure pipeline beats in timer
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2023-11-21 15:55:23 +01:00 |
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39ca47aea9
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FPGA: Add processing stalls
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2023-11-21 15:42:26 +01:00 |
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ba70aa1915
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FPGA: Load calibration issues datamover commands first
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2023-11-18 22:44:37 +01:00 |
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e5397e68cf
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FPGA: Clean-up of HDL modules
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2023-11-18 19:18:26 +01:00 |
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b69d9cb477
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FPGA: Fix setup_action.sh
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2023-11-17 16:48:27 +01:00 |
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c66c06e8f5
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FPGA: Fix setup action
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2023-11-02 15:09:04 +01:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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4fbd747341
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FPGA: Remove multipixel from the pipeline
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2023-10-27 20:47:44 +02:00 |
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4978149fdd
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FPGA: Add register slice in the data pipeline
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2023-10-27 19:43:40 +02:00 |
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c896ec5659
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FPGA: Remove bitshuffle from the pipeline
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2023-10-27 19:41:02 +02:00 |
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f46a8e47a0
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FPGA: Use AggressiveExplore for routing
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2023-10-27 19:12:27 +02:00 |
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08c2427fc7
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FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign
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2023-10-27 15:42:24 +02:00 |
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4fbac629d6
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HLS: Use U55C part number for proper usage statistics
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2023-10-27 13:54:35 +02:00 |
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cf69aef472
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FPGA: Add extra register slices for upside_down
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2023-10-26 22:36:08 +02:00 |
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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6bcf54f603
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FPGA: Add bitshuffle to the design (warning! no test for full integration!)
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2023-10-25 11:07:21 +02:00 |
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d408b3ed2a
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FPGA: Integrate add multipixel into the design
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2023-10-24 18:58:59 +02:00 |
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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f04f7a274b
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FPGA: Name spot finder signals in consistent manner
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2023-10-19 20:52:09 +02:00 |
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c7b7abb34d
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FPGA: Remove register slice for strong pixel result
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2023-10-19 12:14:17 +02:00 |
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6f9f918ee6
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HLS: Improve make scripts, so HLS test bench can be defined
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2023-10-18 16:32:31 +02:00 |
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