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30599e2858
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Fix bug in detector initialize
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2024-03-23 04:07:12 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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d82bd13917
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Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
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2023-12-14 22:39:17 +01:00 |
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0b69dfb290
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New REST+OpenAPI interface
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2023-12-11 12:11:54 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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d2f1c569a7
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FPGA: Modify FPGA register map (move action configuration to offset 0x200)
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2023-11-21 15:24:55 +01:00 |
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8635724ca3
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Move FPGA register map from Definitions.h to jfjoch_drv.h
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2023-11-21 15:20:12 +01:00 |
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1e6f64b4da
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FPGA: Increase max summation to 256
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2023-11-16 21:32:37 +01:00 |
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98cb58d199
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PCIe driver: Fix addresses for calibration and frame generator
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2023-11-08 14:36:36 +01:00 |
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f21f226a59
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Move MAX_FPGA_SUMMATION to Definitions.h
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2023-11-02 12:55:52 +01:00 |
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b3eceef7cd
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FPGA: Max module number is 32
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2023-11-01 15:55:06 +01:00 |
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112a62fc7f
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FPGA: remove limit of modules for frame_generator
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2023-11-01 14:20:43 +01:00 |
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3940f067a8
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MAX_MODULES_FPGA moved to Definitions.h => This needs to be const for RELEASE_LEVEL
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2023-11-01 13:16:22 +01:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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2268486824
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HLS: Added frame_summation core
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2023-10-26 22:31:09 +02:00 |
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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e1a6830c50
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FPGA: Add multipixel (-> TODO calculate proper number)
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2023-10-24 16:43:24 +02:00 |
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4e4a232a6d
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Definitions: Increase max gRPC message size to 2 GB -> need to change later how calibration is being transferred
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2023-10-20 11:40:09 +02:00 |
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6691b01265
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PCIe driver: accept spot finding parameters
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2023-10-18 21:23:41 +02:00 |
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98fe70315b
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FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design)
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2023-09-30 11:28:01 +02:00 |
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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f4f4b50be7
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FPGA: frame_generator has 8 module specific frames
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2023-09-24 15:43:04 +02:00 |
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f06e92fd1b
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FPGA: load_calibration allows to upload integration map
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2023-09-22 18:28:35 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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a5aed37100
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Definitions.h: Increase space for data processing results
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2023-09-21 10:08:53 +02:00 |
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8c1bc9d89d
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FPGA: Remove non-blocking mode
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2023-09-20 16:41:14 +02:00 |
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7396ee342c
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FPGA: Increase release level to make sure FPGA is using 1 MiB bursts only
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2023-09-19 13:13:23 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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0b95456d3d
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Adapt PCIe driver and tests for the new frame generator
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2023-09-13 21:44:20 +02:00 |
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7a635f1ee8
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FPGA: load_calibration clean-up + simplification
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2023-09-12 09:16:45 +02:00 |
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6251c58f32
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FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
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2023-09-08 19:08:37 +02:00 |
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3aeb3e09ee
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FPGA: Do not load internal packet generator frame via DMA
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2023-09-06 11:57:16 +02:00 |
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2f7b46290a
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FPGA: Enable non-power of 2 storage cell number
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2023-07-04 21:59:48 +02:00 |
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4ce2fcf98f
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DiffractionExperiment: Adjust storage cell delay as a parameter
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2023-07-04 21:07:40 +02:00 |
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3067604e2a
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Definitions.h: shortest allowed count time is 5 us
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2023-07-04 16:37:56 +02:00 |
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47330228ef
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Use data_collection_id to detect issues in work completion queue
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2023-05-31 12:23:22 +02:00 |
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b868a24dad
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FPGA: Minor improvements to internal_packet_generator - should now better break in case of cancellation
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2023-05-31 11:08:28 +02:00 |
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c1212a14d9
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FPGA: work requests are consumed while host_writer not working
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2023-05-26 22:12:34 +02:00 |
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021e652dc6
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FPGA: non-blocking mode (to be tested)
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2023-05-26 18:46:26 +02:00 |
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c2b42916c2
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FPGA: host_writer allows to skip frames, if no available location in host memory
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2023-05-24 11:54:51 +02:00 |
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7d5694139f
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FPGA: Save full JF timestamp and exptime
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2023-05-17 21:30:42 +02:00 |
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e8e5f50b21
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Max summation is 5000
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2023-05-08 13:12:44 +02:00 |
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653b82d6c3
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FPGA + receiver + detector: Use column ID to decode detector half-module number
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2023-04-15 11:08:32 +02:00 |
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1757d42182
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Initial commit
Signed-off-by: Filip Leonarski <filip.leonarski@psi.ch>
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2023-04-06 11:17:59 +02:00 |
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