new address map, changed recorder and segment memory

measurement by common lib

Changelog.md

@@ -1,3 +1,8 @@
+## 3.0
+* Added Simulation
+* Added Decoder streaming output
+* Changed Register and Memory Address Map
+
 ## 2.2
 
 * Added Features  

README.md

@@ -3,12 +3,14 @@ The EVR320 Embedded Event Receiver (EEVR) is able to connect with a MRF Timing S
 Mainly the EEVR is used to decode configurable events and use them in firmware as triggers. 
 
 ## Maintainer
-Patric Bucher [patric.bucher@psi.ch]  
+Patric Bucher [patric.bucher@psi.ch] 
+Jonas Purtschert [jonas.purtschert@psi.ch]  
 
 ## Authors
 Waldemar Koprek [waldemar.koprek@psi.ch]  
 Goran Marinkovic [goran.marinkovic@psi.ch]  
 Patric Bucher [patric.bucher@psi.ch]  
+Jonas Purtschert [jonas.purtschert@psi.ch]  
 
 ## Documentation
 See [EVR320 Documentation](doc/evr320.pdf "doc/evr320.pdf")  
@@ -29,10 +31,13 @@ Examples for things that do not belong into this library:
 ## Dependencies
 
 ### Synthesis
-- none  
+- Libraries/Firmware/VHDL/psi\_common (https://github.com/paulscherrerinstitute/psi_common) 
 
 ### Simulation
 - Libraries/Firmware/TCL/PsiSim  
+- Libraries/Firmware/VHDL/psi\_common (https://github.com/paulscherrerinstitute/psi_common) 
+- Libraries/Firmware/VHDL/UVVM (https://github.com/UVVM/UVVM) 
+
 
 ### with IFC1210 Bindings
 - Libraries/BoardSupport/IFC1210/tosca2

constraints/eevr.ucf

@@ -0,0 +1,6 @@
+# FIFO clock crossing for streaming interface:
+# constrain to have less delay than one clock cycle of the faster clock:
+
+set_max_delay -datapath_only -from <ClkA> -to <ClkB> <faster_clock_period>
+set_max_delay -datapath_only -from <ClkB> -to <ClkA> <faster_clock_period>
+

hdl/evr320_data_filter.vhd

@@ -0,0 +1,68 @@
+------------------------------------------------------------------------------
+--  Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
+--  All rights reserved.
+--  Project:      evr320
+--  Authors:      Jonas Purtschert
+--  Description:  Filter a specific data field from data buffer stream of the decoder:
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_1164.all;
+
+entity evr320_data_filter is
+  generic (
+    ADDRESS   : std_logic_vector(11 downto 0);
+    NUM_BYTES : integer := 8
+  );
+  port (
+    -- User stream interface
+    i_stream_clk        : in    std_logic;                          -- user clock
+    i_stream_data       : in    std_logic_vector(7 downto 0);  
+    i_stream_addr       : in    std_logic_vector(10 downto 0);  
+    i_stream_valid      : in    std_logic;
+    -- filter output:
+    o_data              : out   std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
+    o_valid             : out   std_logic := '0'
+  );
+end evr320_data_filter;
+
+
+architecture behavioral of evr320_data_filter is
+
+  signal data_shift : std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
+  signal match : std_logic := '0';
+  signal shift_cnt : integer range 0 to NUM_BYTES;
+
+begin
+  process(i_stream_clk)
+    variable addr : std_logic_vector(10 downto 0) := (others=>'0');
+    variable data : std_logic_vector(7 downto 0) := (others=>'0');
+  begin
+     if (rising_edge(i_stream_clk)) then
+       o_valid <= '0';
+
+       if (i_stream_valid = '1') then
+         addr := i_stream_addr;
+         data := i_stream_data;
+
+         if (addr = ADDRESS(10 downto 0) or match = '1') then
+           match <= '1';
+           if (shift_cnt < NUM_BYTES) then
+             data_shift <= data_shift((data_shift'high - data'length) downto 0) & data;
+             shift_cnt <= shift_cnt + 1;
+           else    -- all data fetched, send to out
+             match <= '0';
+             shift_cnt <= 0;
+             o_valid <= '1';
+             o_data <= data_shift;
+           end if;
+         end if; -- if addr match
+       end if;   -- if valid
+
+     end if;
+  end process;
+
+end behavioral;

hdl/evr320_decoder.vhd

@@ -18,9 +18,9 @@ use ieee.std_logic_misc.all;
 library unisim;
 use unisim.vcomponents.all;
 
+library work;
 use work.evr320_pkg.all;
 
-
 entity evr320_decoder is
    generic
    (
@@ -48,9 +48,16 @@ entity evr320_decoder is
       i_evr_params                : in    typ_evr320_params;
       o_event_recorder_stat       : out   typ_evt_rec_status;
       i_event_recorder_ctrl       : in    typ_evt_rec_ctrl;
-      i_mem_addr                  : in    std_logic_vector(11 downto  0);
+      i_mem_addr                  : in    std_logic_vector(13 downto  0);
       o_mem_data                  : out   std_logic_vector(MEM_DATA_WIDTH - 1 downto  0);
       --------------------------------------------------------------------------
+      -- User stream interface User clock
+      --------------------------------------------------------------------------
+      i_stream_clk                : in    std_logic;
+      o_stream_data               : out   std_logic_vector(7 downto 0); 
+      o_stream_addr               : out   std_logic_vector(10 downto 0); 
+      o_stream_valid              : out   std_logic;
+      --------------------------------------------------------------------------
       -- User interface MGT clock
       --------------------------------------------------------------------------
       o_usr_events                : out   std_logic_vector( 3 downto  0);
@@ -165,17 +172,13 @@ architecture behavioral of evr320_decoder is
    constant mem_ctrl_rd                 : std_logic_vector( 1 downto  0) := "11";
    signal   mem_fsm                     : std_logic_vector( 1 downto  0) := "00";
    -- Data memory address
-   signal   mem_addr                    : std_logic_vector(11 downto  0);   
+   signal   mem_addr                    : std_logic_vector(13 downto  0);   
    -- Data memory write      
    signal   mem_data_wren               : std_logic := '0';
    signal   mem_data_wr_addr            : std_logic_vector(10 downto  0) := (others => '0');
    signal   mem_data_wr_byte            : std_logic_vector( 7 downto  0) := (others => '0');
    -- Data memory read      
    signal   mem_data_dpram              : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
-   signal   mem_data_event0             : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
-   signal   mem_data_event1             : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
-   signal   mem_data_event2             : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
-   signal   mem_data_event3             : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
    -- Event Recorder
    signal   sos_event                   : std_logic_vector(  3 downto  0) := (others => '0');
    signal   usr_events_save             : std_logic := '0';
@@ -203,7 +206,7 @@ architecture behavioral of evr320_decoder is
    signal   mem_data_event_nr_timestamp : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
    signal   mem_data_dpram_sos          : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
    signal   mem_data_segment_timestamp  : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
-   
+   signal   stream_raw                  : std_logic_vector(18 downto 0);  
 --   attribute safe_implementation: string;
 --   attribute safe_implementation of frame_fsm : signal is "yes";
 --   attribute safe_implementation of mem_fsm   : signal is "yes";
@@ -220,7 +223,7 @@ begin
    debug_clk                      <= i_mgt_rx_clk;
    debug( 15 downto   0)          <= i_mgt_rx_data;
    debug( 17 downto  16)          <= i_mgt_rx_charisk;
-   debug( 18)                     <= '0';
+   debug( 23 downto  18)          <= (others=>'0');
    debug( 31 downto  24)          <= (others => '0');
    debug( 35 downto  32)          <= "0001" when (frame_fsm = frame_idle    ) else
                                      "0010" when (frame_fsm = frame_addr_gap) else
@@ -265,7 +268,7 @@ begin
    -- Address Alignment for 32/64-bit Data Width
    -----------------------------------------------------------------------------
    gen_addr_align64: if MEM_DATA_WIDTH = 64 generate
-      mem_addr <= i_mem_addr(10 downto 0) & '0';
+      mem_addr <= i_mem_addr(12 downto 0) & '0';
    end generate gen_addr_align64;
    
    gen_addr_align32: if MEM_DATA_WIDTH = 32 generate
@@ -700,12 +703,12 @@ begin
    -----------------------------------------------------------------------------
    -- Data memory selector
    -----------------------------------------------------------------------------
-   o_mem_data                     <= mem_data_dpram   when (mem_addr(11 downto 9) = "000") else
-                                     mem_data_event0  when (mem_addr(11 downto 9) = "001") else
-                                     mem_data_event1  when (mem_addr(11 downto 9) = "010") else
-                                     mem_data_event2  when (mem_addr(11 downto 9) = "011") else
-                                     mem_data_event3  when (mem_addr(11 downto 9) = "100") else
-                                     mem_data_event_recorder;
+   -- Memory Map (byte-address):
+   -- * Segmented Data Buffer:  0x9000 - 0x97FF
+   -- * Event Recorder:         0xB000 - 0xBFFF
+   o_mem_data                     <= mem_data_dpram           when (mem_addr(13 downto 9)  = "10010") else
+                                     mem_data_event_recorder  when (mem_addr(13 downto 10) = "1011") else
+                                     x"DEADC0DE";
 
    -----------------------------------------------------------------------------
    -- Data Memory
@@ -733,100 +736,54 @@ begin
       dob                         => mem_data_dpram
    );
 
-   -----------------------------------------------------------------------------
-   -- Data Memory
-   -- write port - timing decoder
-   -- read port  - usr domain
-   -----------------------------------------------------------------------------
-   evr320_event0_inst: entity work.evr320_buffer
-   generic map
-   (
-      MEM_SIZE_BYTE               => 2048,
-      MEM_DOB_WIDTH               => MEM_DATA_WIDTH
-   )
-   port map
-   (
-      -- port a
-      clka                        => i_mgt_rx_clk,
-      ena                         => HIGH,
-      wea                         => mem_data_wren,
-      addra                       => mem_data_wr_addr,
-      dia                         => mem_data_wr_byte,
-      page                        => usr_events( 0)( 3),
-      -- port b
-      clkb                        => i_usr_clk,
-      enb                         => HIGH,
-      addrb                       => mem_addr( 8 downto MEM_ADDR_LSB),
-      dob                         => mem_data_event0
-   );
+  -------------------------------------------------------------------------
+  -- async fifo for streaming interface 
+  -------------------------------------------------------------------------
+    strm_fifo_inst : entity work.psi_common_async_fifo
+    generic map (
+      Width_g         => 11+8,
+      Depth_g         => 2048,
+      AlmFullOn_g     => false,
+      AlmFullLevel_g  => 2,
+      AlmEmptyOn_g    => false,
+      AlmEmptyLevel_g => 2,
+      RamStyle_g      => "WBR",
+      RamBehavior_g   => "block" -- auto, distributed
+    )
+    port map (
+      -- Control Ports
+      InClk   => i_mgt_rx_clk,
+      InRst   => i_mgt_rst,
+      OutClk  => i_stream_clk,
+      OutRst  => '0',
+      
+      -- Input Data
+      InData  => mem_data_wr_addr & mem_data_wr_byte,
+      InVld   => mem_data_wren,
+      InRdy   => open,
+      
+      -- Output Data
+      OutData   => stream_raw,
+      OutVld    => o_stream_valid,
+      OutRdy    => '1',
+      
+      -- Input Status
+      InFull    => open,
+      InEmpty   => open,
+      InAlmFull   => open,
+      InAlmEmpty  => open,
+      InLevel   => open,
+      
+      -- Output Status
+      OutFull   => open,
+      OutEmpty  => open,
+      OutAlmFull  => open,
+      OutAlmEmpty => open,
+      OutLevel  => open
+    );  
 
-   evr320_event1_inst: entity work.evr320_buffer
-   generic map
-   (
-      MEM_SIZE_BYTE               => 2048,
-      MEM_DOB_WIDTH               => MEM_DATA_WIDTH
-   )
-   port map
-   (
-      -- port a
-      clka                        => i_mgt_rx_clk,
-      ena                         => HIGH,
-      wea                         => mem_data_wren,
-      addra                       => mem_data_wr_addr,
-      dia                         => mem_data_wr_byte,
-      page                        => usr_events( 1)( 3),
-      -- port b
-      clkb                        => i_usr_clk,
-      enb                         => HIGH,
-      addrb                       => mem_addr( 8 downto MEM_ADDR_LSB),
-      dob                         => mem_data_event1
-   );
-
-   evr320_event2_inst: entity work.evr320_buffer
-   generic map
-   (
-      MEM_SIZE_BYTE               => 2048,
-      MEM_DOB_WIDTH               => MEM_DATA_WIDTH
-   )
-   port map
-   (
-      -- port a
-      clka                        => i_mgt_rx_clk,
-      ena                         => HIGH,
-      wea                         => mem_data_wren,
-      addra                       => mem_data_wr_addr,
-      dia                         => mem_data_wr_byte,
-      page                        => usr_events( 2)( 3),
-      -- port b
-      clkb                        => i_usr_clk,
-      enb                         => HIGH,
-      addrb                       => mem_addr( 8 downto MEM_ADDR_LSB),
-      dob                         => mem_data_event2
-   );
-
-   evr320_event3_inst: entity work.evr320_buffer
-   generic map
-   (
-      MEM_SIZE_BYTE               => 2048,
-      MEM_DOB_WIDTH               => MEM_DATA_WIDTH
-   )
-   port map
-   (
-      -- port a
-      clka                        => i_mgt_rx_clk,
-      ena                         => HIGH,
-      wea                         => mem_data_wren,
-      addra                       => mem_data_wr_addr,
-      dia                         => mem_data_wr_byte,
-      page                        => usr_events( 3)( 3),
-      -- port b
-      clkb                        => i_usr_clk,
-      enb                         => HIGH,
-      addrb                       => mem_addr( 8 downto MEM_ADDR_LSB),
-      dob                         => mem_data_event3
-   );
-   
-   
+    o_stream_data <= stream_raw(7 downto 0);
+    o_stream_addr <= stream_raw(18 downto 8);
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    -- EVENT RECORDER
@@ -970,11 +927,11 @@ begin
       --------------------------------------------------------------------------
       -- Memory Selector Event Recorder
       --------------------------------------------------------------------------
-      mem_data_event_recorder     <= mem_data_dpram_sos           when (mem_addr(11 downto  9) = B"101")     else  -- 2K
-                                     mem_data_event_nr_timestamp  when (mem_addr(11 downto  8) = B"1100")    else  -- 1K
-                                     mem_data_segment_timestamp   when (mem_addr(11 downto  7) = B"1101_0")  else  -- 512B
-                                     mem_data_event_nr            when (mem_addr(11 downto  6) = B"1101_10") else  -- 256B
-                                     mem_data_event_flag          when (mem_addr(11 downto  6) = B"1101_11") else  -- 256B
+      mem_data_event_recorder     <= mem_data_dpram_sos           when (mem_addr(13 downto 9) = B"1011_0")   else  -- 2K
+                                     mem_data_event_nr_timestamp  when (mem_addr(13 downto 8) = B"1011_10")  else  -- 1K
+                                     mem_data_segment_timestamp   when (mem_addr(13 downto 7) = B"1011_110") else  -- 512B
+                                     mem_data_event_nr            when (mem_addr(13 downto 6) = B"1011_1110") else  -- 256B
+                                     mem_data_event_flag          when (mem_addr(13 downto 6) = B"1011_1111") else  -- 256B
                                      (others => '0');
    
    
@@ -1081,7 +1038,6 @@ begin
          dob                         => mem_data_event_nr
       ); 
 
-      
       --------------------------------------------------------------------------
       -- Event Flags of all Events
       --------------------------------------------------------------------------
@@ -1127,4 +1083,4 @@ end behavioral;
 
 --------------------------------------------------------------------------------
 -- End of file
---------------------------------------------------------------------------------
+--------------------------------------------------------------------------------

hdl/evr320_ifc1210_wrapper.vhd

@@ -24,7 +24,8 @@ entity evr320_ifc1210_wrapper is
   generic(
     g_MGT_LOCATION                : string                        := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
     g_FACILITY                    : string                        := "SFEL";        -- "HIPA" | "SFEL"
-    g_EVENT_RECORDER              : boolean                       := false          -- enable/disable Event Recorder functionality
+    g_EVENT_RECORDER              : boolean                       := false;         -- enable/disable Event Recorder functionality
+    g_XUSER_CLK_FREQ              : natural                       := 125000000      -- Xuser Clk Frequency in Hz
   );
   port(
     tick1sec_i                    : in    std_logic;      
@@ -36,13 +37,13 @@ entity evr320_ifc1210_wrapper is
     -- ------------------------------------------------------------------------
     -- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
     -- ------------------------------------------------------------------------
-    xuser_CLK                     : in    std_logic; 
-    xuser_RESET                   : in    std_logic;                    
-    xuser_TMEM_ENA                : in    std_logic;    
-    xuser_TMEM_WE                 : in    std_logic_vector( 7 downto 0);                  
-    xuser_TMEM_ADD                : in    std_logic_vector(13 downto 3); 
-    xuser_TMEM_DATW               : in    std_logic_vector(63 downto 0);
-    xuser_TMEM_DATR               : out   std_logic_vector(63 downto 0);
+    xuser_CLK:       in    std_logic;
+    xuser_RESET:     in    std_logic;
+    xuser_TMEM_ENA:  in    std_logic;
+    xuser_TMEM_WE:   in    std_logic_vector( 7 downto 0);
+    xuser_TMEM_ADD:  in    std_logic_vector(15 downto 3);
+    xuser_TMEM_DATW: in    std_logic_vector(63 downto 0);
+    xuser_TMEM_DATR: out   std_logic_vector(63 downto 0);
     -- ------------------------------------------------------------------------
     -- MGT Interface
     -- ------------------------------------------------------------------------
@@ -60,7 +61,14 @@ entity evr320_ifc1210_wrapper is
     clk_evr_o                     : out   std_logic;                         -- Recovered parallel clock from MGT
     usr_events_o                  : out   std_logic_vector( 3 downto  0);    -- User defined event pulses with one clock cycle length
     usr_events_ext_o              : out   std_logic_vector( 3 downto  0);    -- User defined event pulses with four clock cycle length
-    sos_event_o                   : out   std_logic                          -- Start-of-Sequence Event
+    sos_event_o                   : out   std_logic;                         -- Start-of-Sequence Event
+    --------------------------------------------------------------------------
+    -- Decoder axi stream interface, User clock
+    --------------------------------------------------------------------------
+    stream_clk_i                  : in    std_logic := '0';
+    stream_data_o                 : out   std_logic_vector(7 downto 0);  
+    stream_addr_o                 : out   std_logic_vector(10 downto 0);
+    stream_valid_o                : out   std_logic
   );
 end evr320_ifc1210_wrapper;
 
@@ -91,8 +99,8 @@ architecture rtl of evr320_ifc1210_wrapper is
   signal mgt_reset_tmem_evr               : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
   
   signal mem_clk                          : std_logic;
-  signal mem_addr_evr                     : std_logic_vector(11 downto 0);  
-  signal mem_addr_tosca                   : std_logic_vector(10 downto 0); 
+  signal mem_addr_evr                     : std_logic_vector(13 downto 0);  
+  signal mem_addr_tosca                   : std_logic_vector(12 downto 0); 
   signal mem_data                         : std_logic_vector(c_TOSCA2_DATA_WIDTH-1 downto 0);
   
   signal evr_params                       : typ_evr320_params;
@@ -103,8 +111,6 @@ architecture rtl of evr320_ifc1210_wrapper is
   signal event_recorder_control_sync      : typ_evt_rec_ctrl;
   signal event_recorder_control_xuser     : typ_evt_rec_ctrl;
   
-  signal evr_counter_rst                  : std_logic_vector( 2 downto 0) := (others => '0');
-  signal evr_clk_counter                  : std_logic_vector(31 downto 0) := (others => '0');
   signal evr_frequency                    : std_logic_vector(31 downto 0) := (others => '0');
   
   signal debug_data                       : std_logic_vector(127 downto 0);
@@ -179,6 +185,11 @@ begin
       i_event_recorder_ctrl       => event_recorder_control,
       i_mem_addr                  => mem_addr_evr,
       o_mem_data                  => mem_data,
+      -- user stream interface, user clock
+      i_stream_clk                => stream_clk_i,
+      o_stream_data               => stream_data_o, 
+      o_stream_addr               => stream_addr_o, 
+      o_stream_valid              => stream_valid_o,
       -- User interface MGT clock
       o_usr_events                => usr_events_o,
       o_usr_events_ext            => usr_events_ext_o,
@@ -235,24 +246,20 @@ begin
     mem_data_i                    => mem_data
   );
   
-
   -- --------------------------------------------------------------------------
   -- Measure EVR Clock (based on xuser_CLK)
   -- --------------------------------------------------------------------------
-  prc_count_cycles: process(clk_evr)
-  begin
-    if rising_edge(clk_evr) then      
-      if (evr_counter_rst(2 downto 1) = "01") then
-        evr_frequency               <= evr_clk_counter;
-        evr_clk_counter             <= (others => '0');
-      else
-        evr_clk_counter             <= evr_clk_counter + X"0000_0001";
-      end if;
-      -- sync reset and detect edge
-      evr_counter_rst <= evr_counter_rst(1 downto 0) & tick1sec_i;
-    end if;
-  end process;
-
+  clock_meas_inst : entity work.psi_common_clk_meas
+  generic map (
+    MasterFrequency_g  => g_XUSER_CLK_FREQ,
+    MaxMeasFrequency_g => 150000000
+  )
+  port map (
+    ClkMaster   => xuser_CLK,
+    Rst         => xuser_RESET,
+    ClkTest     => clk_evr,
+    FrequencyHz => evr_frequency
+  );
 
   -- --------------------------------------------------------------------------
   -- port mapping
@@ -266,4 +273,4 @@ begin
 end rtl;
 -- ----------------------------------------------------------------------------
 -- ////////////////////////////////////////////////////////////////////////////
--- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------

hdl/evr320_pkg.vhd

@@ -60,7 +60,10 @@ package evr320_pkg is
                                                             data_error          => '0',
                                                             usr_events_counter  => (others =>'0'));
                                                             
-                                                            
+  constant c_INIT_EVT_REC_CTRL : typ_evt_rec_ctrl :=  ( event_number  => (others=>'0'),
+                                                        event_enable  => '0',
+                                                        data_ack      => '0',
+                                                        error_ack     => '0');
   -- --------------------------------------------------------------------------
   -- Function Prototypes
   -- --------------------------------------------------------------------------
@@ -95,4 +98,4 @@ package body evr320_pkg is
 end package body evr320_pkg;
 --------------------------------------------------------------------------------
 -- End of file
---------------------------------------------------------------------------------
+--------------------------------------------------------------------------------

hdl/evr320_tmem.vhd

@@ -29,7 +29,7 @@ entity evr320_tmem is
     xuser_RESET                   : in    std_logic;                    
     xuser_TMEM_ENA                : in    std_logic;    
     xuser_TMEM_WE                 : in    std_logic_vector( 7 downto 0);                  
-    xuser_TMEM_ADD                : in    std_logic_vector(13 downto 3); 
+    xuser_TMEM_ADD                : in    std_logic_vector(15 downto 3); 
     xuser_TMEM_DATW               : in    std_logic_vector(63 downto 0);
     xuser_TMEM_DATR               : out   std_logic_vector(63 downto 0);
     ---------------------------------------------------------------------------
@@ -42,7 +42,7 @@ entity evr320_tmem is
     mgt_status_i                  : in    std_logic_vector(31 downto  0);          
     mgt_reset_o                   : out   std_logic;          
     mem_clk_o                     : out   std_logic; 
-    mem_addr_o                    : out   std_logic_vector(10 downto  0); 
+    mem_addr_o                    : out   std_logic_vector(12 downto  0); 
     mem_data_i                    : in    std_logic_vector(63 downto  0)
   );
 end evr320_tmem;
@@ -58,7 +58,6 @@ architecture rtl of evr320_tmem is
   constant TMEM_ADDR_LSB          : integer := 3; -- 64 bit
   constant REG_ADDR_WIDTH         : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
   constant REG_ADDR_MSB           : integer := REG_ADDR_WIDTH - 1;
-  constant MEM_ADDR_START         : std_logic_vector(7 downto  0) := X"10";
   
 
   
@@ -68,7 +67,7 @@ architecture rtl of evr320_tmem is
   -- xuser tmem signals
   signal xuser_TMEM_WE_reg      : std_logic_vector( 7 downto 0)   := (others => '0');
   signal xuser_TMEM_ENA_reg     : std_logic                       := '0';
-  signal xuser_TMEM_ADD_reg     : std_logic_vector(13 downto 3)   := (others => '0');
+  signal xuser_TMEM_ADD_reg     : std_logic_vector(15 downto 3)   := (others => '0');
   signal xuser_TMEM_DATW_reg    : std_logic_vector(63 downto 0)   := (others => '0');
   
   -- evr params
@@ -146,7 +145,7 @@ begin
   begin
     if (rising_edge(xuser_CLK)) then
       if (xuser_TMEM_ENA_reg = '1') then
-        if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0) then
+        if (xuser_TMEM_ADD_reg(15 downto REG_ADDR_WIDTH) = 0) then
           case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
             when X"0" =>    xuser_TMEM_DATR <=  event_numbers_concat          & X"0000" & mgt_status_evr;           -- 64bit / ByteAddr 000
             when X"1" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)        & X"0000_00" & bit2byte(mgt_reset);   -- 64bit / ByteAddr 008   --> 0x00C = not implemented in ifc1210
@@ -180,7 +179,7 @@ begin
       er_error_ack  <= er_error_ack(2 downto 0) & '0';
 
       
-      if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0)  then
+      if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(15 downto REG_ADDR_WIDTH) = 0)  then
         -----------------------------------------------------------------------------------------------------------------
         if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
        -- if xuser_TMEM_WE_reg(0) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
@@ -246,7 +245,7 @@ begin
   -- Port mapping                                                       
   -- --------------------------------------------------------------------------
   mem_clk_o               <= xuser_CLK;
-  mem_addr_o              <= xuser_TMEM_ADD - MEM_ADDR_START;
+  mem_addr_o              <= xuser_TMEM_ADD;
   evr_params_o            <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
   evr_evt_rec_control_o   <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
   mgt_reset_o             <= mgt_reset;
@@ -256,4 +255,4 @@ begin
 end rtl;
 -- ----------------------------------------------------------------------------
 -- ////////////////////////////////////////////////////////////////////////////
--- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------

hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd

@@ -284,7 +284,7 @@ begin
     )
     port map   (
       ------------------------ Loopback and Powerdown Ports ----------------------
-      LOOPBACK                        =>      i_mgt.ctrl.LOOPBACK,                            --tied_to_ground_vec_i(2 downto 0),
+      LOOPBACK                        =>      i_mgt.CTRL.LOOPBACK,                            --tied_to_ground_vec_i(2 downto 0),
       RXPOWERDOWN                     =>      "00",                                           --
       TXPOWERDOWN                     =>      "00",                                           --
       -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------

sim/ci.do

@@ -1,2 +1,2 @@
 source run.tcl
-quit
+#quit

sim/config.tcl

@@ -10,16 +10,26 @@ run_suppress 8684,3479,3813,8009,3812
 
 
 # EVR320 Decoder
-add_sources $LibPath/Libraries/VHDL/evr320/hdl {
+add_sources $LibPath/Firmware/VHDL/evr320/hdl {
 	evr320_pkg.vhd \
 	evr320_buffer.vhd \
 	evr320_dpram.vhd \
 	evr320_timestamp.vhd \
 	evr320_decoder.vhd \
+  evr320_data_filter.vhd \
 } -tag evr320_decoder
 
+# EVR320 Decoder Testbench
+add_sources $LibPath/Firmware/VHDL/evr320/tb {
+	evr320_decoder_tb.vhd \
+} -tag evr320_decoder_tb
+
+# setup tb runs
+create_tb_run "evr320_decoder_tb"
+add_tb_run
+
 # IFC1210 Bindings
-add_sources $LibPath/Libraries/VHDL/evr320/hdl {
+add_sources $LibPath/Firmware/VHDL/evr320/hdl {
 	v6vlx_gtxe1_pkg.vhd \
 	v6vlx_gtxe1_101MHz27_1Gbps0127.vhd \
 	v6vlx_gtxe1_142MHz8_2Gbps856.vhd \
@@ -29,8 +39,21 @@ add_sources $LibPath/Libraries/VHDL/evr320/hdl {
 	evr320_ifc1210_wrapper.vhd \
 } -tag evr320_ifc1210
 
+# psi_common dependency:
+add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
+  psi_common_array_pkg.vhd \
+  psi_common_math_pkg.vhd \
+  psi_common_logic_pkg.vhd \
+  psi_common_sdp_ram.vhd \
+  psi_common_pulse_cc.vhd \
+  psi_common_async_fifo.vhd \
+  psi_common_clk_meas.vhd \
+} -tag psi_common
+
 # tosca2_glb_pkg dependency
 add_library tosca2
-add_sources $LibPath/Libraries/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
+
+add_sources $LibPath/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
   tosca2_glb_pkg.vhd \
-}
+}
+

sim/run.tcl

@@ -1,8 +1,42 @@
 # Library Path
-set LibPath "../../../../"
+set LibPath "../../../.."
 
-#Load dependencies
-source $LibPath/Libraries/TCL/PsiSim/PsiSim.tcl
+# Compile UVVM library (if necessary):
+# -------------------------------------------------------
+set uvvm_lib $LibPath/Firmware/VHDL/UVVM/uvvm_util/sim/uvvm_util/
+# compile lib if folder not exist:
+#if {![file isdirectory $uvvm_lib]} { 
+  # copy adapted pkg:
+  file copy -force ../tb/adaptations_pkg.vhd $LibPath/Firmware/VHDL/UVVM/uvvm_util/src/
+  set last_dir [pwd]
+  cd $LibPath/Firmware/VHDL/UVVM/uvvm_util/script/
+  do compile_src.do
+  cd $last_dir
+#}
+vmap uvvm_util $LibPath/Firmware/VHDL/UVVM/uvvm_util/sim/uvvm_util/
+# -------------------------------------------------------
+
+
+# Check if running in jenkins environment
+if [info exists env(JENKINS_HOME)] {
+    set jenkins 1
+} else {
+    set jenkins 0
+}
+
+# map different libraries when running on jenkins machine:
+if {$jenkins == 1} {
+    vmap unisim /home/modelsim/xilinx_libs/13.4/unisim
+    vmap xilinxcorelib /home/modelsim/xilinx_libs/13.4/xilinxcorelib
+    vmap secureip /home/modelsim/xilinx_libs/13.4/secureip
+} else {
+    vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
+    vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/xilinxcorelib
+    vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim 
+}
+
+#Load dependencies TODO
+source $LibPath/Firmware/TCL/PsiSim/PsiSim.tcl
 
 #Import psi::sim library
 namespace import psi::sim::*
@@ -18,8 +52,12 @@ puts "------------------------------"
 puts "-- Compile"
 puts "------------------------------"
 clean_libraries -all
+compile_files -tag psi_common
 compile_files -tag evr320_decoder
-#compile_files -lib tosca2
+compile_files -tag evr320_decoder_tb
+compile_files -lib tosca2
+compile_files -tag evr320_ifc1210
 #compile_files -lib evr320
 
-run_check_errors "###ERROR###"
+run_tb -all
+run_check_errors "###ERROR###"

tb/adaptations_pkg.vhd

@@ -0,0 +1,290 @@
+--========================================================================================================================
+-- Copyright (c) 2017 by Bitvis AS.  All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- Description   : See library quick reference (under 'doc') and README-file(s)
+------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use std.textio.all;
+
+
+use work.types_pkg.all;
+
+package adaptations_pkg is
+  constant C_ALERT_FILE_NAME : string := "_Alert.txt";
+  constant C_LOG_FILE_NAME   : string := "_Log.txt";
+
+  constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO         : boolean := false;  -- Set this to false when you no longer need the initial info
+  constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := false;  -- Set this to false when you no longer need the release info
+
+  -------------------------------------------------------------------------------
+  -- Log format
+  -------------------------------------------------------------------------------
+  --UVVM: [<ID>]  <time>  <Scope>        Msg
+  --PPPPPPPPIIIIII TTTTTTTT  SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
+  constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters
+
+  constant C_LOG_PREFIX_WIDTH   : natural := C_LOG_PREFIX'length;
+  constant C_LOG_MSG_ID_WIDTH   : natural := 18;
+  constant C_LOG_TIME_WIDTH     : natural := 14; -- 3 chars used for unit eg. " ns"
+  constant C_LOG_TIME_BASE      : time    := ns; -- Unit in which time is shown in log (ns | ps)
+  constant C_LOG_TIME_DECIMALS  : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
+  constant C_LOG_SCOPE_WIDTH    : natural := 16;
+  constant C_LOG_LINE_WIDTH     : natural := 200;
+  constant C_LOG_INFO_WIDTH     : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
+
+  constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
+  constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r'
+                                                      -- is the first character of the string.
+                                                      -- All others '\r' will be printed as is.
+
+  constant C_SINGLE_LINE_ALERT  : boolean := false; -- If true prints alerts on a single line.
+  constant C_SINGLE_LINE_LOG    : boolean := false; -- If true prints log messages on a single line.
+
+  constant C_TB_SCOPE_DEFAULT : string := "TB_SCOPE"; -- Default scope in test sequencer
+
+  constant C_LOG_TIME_TRUNC_WARNING : boolean := false; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
+  constant C_SHOW_LOG_ID            : boolean := true; -- This constant has replaced the global_show_log_id
+  constant C_SHOW_LOG_SCOPE         : boolean := true; -- This constant has replaced the global_show_log_scope
+
+  constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false;
+
+  constant C_USE_STD_STOP_ON_ALERT_STOP_LIMIT : boolean := true; -- true: break using std.env.stop, false: break using failure
+
+  shared variable shared_default_log_destination        : t_log_destination  := CONSOLE_AND_LOG;
+
+
+  -------------------------------------------------------------------------------
+  -- Verbosity control
+  -- NOTE: Do not enter new IDs without proper evaluation:
+  --       1. Is it - or could it be covered by an existing ID
+  --       2. Could it be combined with other needs for a more general new ID
+  --       Feel free to suggest new ID for future versions of UVVM Utility Library (support@bitvis.no)
+  -------------------------------------------------------------------------------
+  type t_msg_id is (
+    -- Bitvis utility methods
+    NO_ID,                -- Used as default prior to setting actual ID when transfering ID as a field in a record
+    ID_UTIL_BURIED,       -- Used for buried log messages where msg and scope cannot be modified from outside
+    ID_BITVIS_DEBUG,      -- Bitvis internal ID used for UVVM debugging
+    ID_UTIL_SETUP,        -- Used for Utility setup
+    ID_LOG_MSG_CTRL,      -- Used inside Utility library only - when enabling/disabling msg IDs.
+    ID_ALERT_CTRL,        -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
+    ID_NEVER,             -- Used for avoiding log entry. Cannot be enabled.
+    ID_FINISH_OR_STOP,            -- Used when terminating the complete simulation - independent of why
+    ID_CLOCK_GEN,         -- Used for logging when clock generators are enabled or disabled
+    ID_GEN_PULSE,         -- Used for logging when a gen_pulse procedure starts pulsing a signal
+    ID_BLOCKING,          -- Used for logging when using synchronisation flags
+    -- General
+    ID_POS_ACK,           -- To write a positive acknowledge on a check
+    -- Directly inside test sequencers
+    ID_LOG_HDR,           -- ONLY allowed in test sequencer, Log section headers
+    ID_LOG_HDR_LARGE,     -- ONLY allowed in test sequencer, Large log section headers
+    ID_LOG_HDR_XL,        -- ONLY allowed in test sequencer, Extra large log section headers
+    ID_SEQUENCER,         -- ONLY allowed in test sequencer, Normal log (not log headers)
+    ID_SEQUENCER_SUB,     -- ONLY allowed in test sequencer, Subprograms defined in sequencer
+    -- BFMs
+    ID_BFM,               -- Used inside a BFM (to log BFM access)
+    ID_BFM_WAIT,          -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
+    ID_BFM_POLL,          -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until())
+    ID_BFM_POLL_SUMMARY,  -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data.
+    ID_TERMINATE_CMD,     -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli
+    -- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
+    -- Segment Ids, finest granularity of packet data
+    ID_SEGMENT_INITIATE,   -- Notify that a packet is about to be transmitted or received
+    ID_SEGMENT_COMPLETE,   -- Notify that a packet has been transmitted or received
+    ID_SEGMENT_HDR,        -- AS ID_SEGMENT_COMPLETE, but also writes header info
+    ID_SEGMENT_DATA,       -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge)
+    -- Packet Ids, medium granularity of packet data
+    ID_PACKET_INITIATE,   -- Notify that a packet is about to be transmitted or received
+    ID_PACKET_COMPLETE,   -- Notify that a packet has been transmitted or received
+    ID_PACKET_HDR,        -- AS ID_PACKET_COMPLETED, but also writes header info
+    ID_PACKET_DATA,       -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge)
+    -- Frame Ids, roughest granularity of packet data
+    ID_FRAME_INITIATE,     -- Notify that a packet is about to be transmitted or received
+    ID_FRAME_COMPLETE,    -- Notify that a packet has been transmitted or received
+    ID_FRAME_HDR,          -- AS ID_FRAME_COMPLETE, but also writes header info
+    ID_FRAME_DATA,         -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge)
+    -- OSVVM Ids
+    ID_COVERAGE_MAKEBIN,  -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin)
+    ID_COVERAGE_ADDBIN,   -- Log messages from AddBin/AddCross
+    ID_COVERAGE_ICOVER,   -- ICover logging, NB: Very low level debugging. Can result in large amount of data.
+    ID_COVERAGE_CONFIG,   -- Logging of configuration in the coverage package
+    ID_COVERAGE_SUMMARY,  -- Report logging : Summary of coverage, with both covered bins and holes
+    ID_COVERAGE_HOLES,    -- Report logging : Holes only
+    -- Distributed command systems
+    ID_UVVM_SEND_CMD,
+    ID_UVVM_CMD_ACK,
+    ID_UVVM_CMD_RESULT,
+    ID_CMD_INTERPRETER,       -- Message from VVC interpreter about correctly received and queued/issued command
+    ID_CMD_INTERPRETER_WAIT,  -- Message from VVC interpreter that it is actively waiting for a command
+    ID_IMMEDIATE_CMD,         -- Message from VVC interpreter that an IMMEDIATE command has been executed
+    ID_IMMEDIATE_CMD_WAIT,    -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
+    ID_CMD_EXECUTOR,          -- Message from VVC executor about correctly received command - prior to actual execution
+    ID_CMD_EXECUTOR_WAIT,     -- Message from VVC executor that it is actively waiting for a command
+    ID_INSERTED_DELAY,        -- Message from VVC executor that it is waiting a given delay
+    -- Distributed data
+    ID_UVVM_DATA_QUEUE,       -- Information about UVVM data FIFO/stack (initialization, put, get, etc)
+    -- VVC system
+    ID_CONSTRUCTOR,           -- Constructor message from VVCs (or other components/process when needed)
+    ID_CONSTRUCTOR_SUB,       -- Constructor message for lower level constructor messages (like Queue-information and other limitations)
+    -- SB package
+    ID_DATA,
+    ID_CTRL,
+    -- Special purpose - Not really IDs
+    ALL_MESSAGES          -- Applies to ALL message ID apart from ID_NEVER
+    );
+  type  t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
+
+  constant C_TB_MSG_ID_DEFAULT : t_msg_id := ID_SEQUENCER; -- msg ID used when calling the log method without any msg ID switch.
+
+  -- Default message Id panel to be used for all message Id panels, except:
+  --  - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT
+  constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
+    ID_NEVER            => DISABLED,
+    ID_UTIL_BURIED      => DISABLED,
+    ID_BITVIS_DEBUG     => DISABLED,
+    ID_COVERAGE_MAKEBIN => DISABLED,
+    ID_COVERAGE_ADDBIN  => DISABLED,
+    ID_COVERAGE_ICOVER  => DISABLED,
+    others              => ENABLED
+  );
+
+  -- If false, OSVVM uses the default message id panel. If true, it uses a separate message id panel.
+  constant C_USE_LOCAL_OSVVM_MSG_ID_PANELS : boolean := TRUE;
+
+  type  t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
+  constant C_MSG_ID_INDENT : t_msg_id_indent := (
+    ID_IMMEDIATE_CMD_WAIT     => "  ..",
+    ID_CMD_INTERPRETER        => "  "   & NUL & NUL,
+    ID_CMD_INTERPRETER_WAIT   => "  ..",
+    ID_CMD_EXECUTOR           => "  "   & NUL & NUL,
+    ID_CMD_EXECUTOR_WAIT      => "  ..",
+    ID_UVVM_SEND_CMD      => "->"   & NUL & NUL,
+    ID_UVVM_CMD_ACK       => "    ",
+    others                => ""     & NUL & NUL & NUL & NUL
+  );
+
+  constant C_MSG_DELIMITER : character := ''';
+
+  -------------------------------------------------------------------------
+  -- Alert counters
+  -------------------------------------------------------------------------
+  -- Default values. These can be overwritten in each sequencer by using
+  -- set_alert_attention or set_alert_stop_limit (see quick ref).
+  constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
+
+  -- 0 = Never stop
+  constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
+                                                       others               => 1);
+
+  -------------------------------------------------------------------------
+  -- Hierarchical alerts
+  -------------------------------------------------------------------------
+  constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false;
+  constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total";
+
+  constant C_EMPTY_NODE : t_hierarchy_node := ("                    ",
+                                                (others => (others => 0)),
+                                                (others => 0),
+                                                (others => true));
+
+  -------------------------------------------------------------------------
+  -- Deprecate
+  -------------------------------------------------------------------------
+  -- These values are used to indicate outdated sub-programs
+  constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
+  shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
+
+
+  ------------------------------------------------------------------------
+  -- UVVM VVC Framework adaptations
+  ------------------------------------------------------------------------
+  constant C_SCOPE          : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
+
+  signal global_show_msg_for_uvvm_cmd  : boolean := true;
+
+  constant C_CMD_QUEUE_COUNT_MAX                     : natural       := 20;  -- (VVC Command queue)  May be overwritten for dedicated VVC
+  constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY      : t_alert_level := WARNING;
+  constant C_CMD_QUEUE_COUNT_THRESHOLD               : natural       := 18;
+  constant C_RESULT_QUEUE_COUNT_MAX                  : natural       := 20;  -- (VVC Result queue)  May be overwritten for dedicated VVC
+  constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY   : t_alert_level := WARNING;
+  constant C_RESULT_QUEUE_COUNT_THRESHOLD            : natural       := 18;
+  constant C_MAX_VVC_INSTANCE_NUM                    : natural       := 20;
+  constant C_MAX_NUM_SEQUENCERS                      : natural       := 10; -- Max number of sequencers
+
+  -- Maximum allowed length of VVC names
+  constant C_MAX_VVC_NAME_LENGTH                     : positive      := 20;
+
+  -- Minimum width of vvc name and channel displayed in scope.
+  -- These combined + the length of instance + 2 (commas), cannot exceed C_LOG_SCOPE_WIDTH.
+  constant C_MINIMUM_CHANNEL_SCOPE_WIDTH             : natural       := 10;
+  constant C_MINIMUM_VVC_NAME_SCOPE_WIDTH            : natural       := 10;
+
+  constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER     : natural := 2048;
+  constant C_NUMBER_OF_DATA_BUFFERS                  : natural := 10;
+
+  -- Default message Id panel intended for use in the VVCs
+  constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
+    ID_NEVER         => DISABLED,
+    ID_UTIL_BURIED   => DISABLED,
+    others           => ENABLED
+  );
+
+  type t_data_source is (     -- May add more types of random ++ later
+    NA,
+    FROM_BUFFER,
+    RANDOM,
+    RANDOM_TO_BUFFER
+  );
+
+  type t_error_injection is (  -- May add more controlled error injection later
+    NA,
+    RANDOM_BIT_ERROR,
+    RANDOM_DATA_ERROR,
+    RANDOM_ADDRESS_ERROR
+  );
+
+  constant C_CMD_IDX_PREFIX : string := " [";
+  constant C_CMD_IDX_SUFFIX : string := "]";
+
+  type t_channel is ( -- NOTE: Add more types of channels when needed for a VVC
+    NA,               -- When channel is not relevant
+    ALL_CHANNELS,     -- When command shall be received by all channels
+    RX,
+    TX);
+
+  constant C_VVCT_ALL_INSTANCES, ALL_INSTANCES : integer := -2;
+  constant ALL_ENABLED_INSTANCES : integer := -3;
+
+  constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500;
+
+  ------------------------------------------------------------------------
+  -- Scoreboard adaptations
+  ------------------------------------------------------------------------
+  constant C_MAX_QUEUE_INSTANCE_NUM : positive := 100; -- Maximum number of instances
+  constant C_SB_TAG_WIDTH           : positive := 128; -- Number of characters in SB tag
+  constant C_SB_SOURCE_WIDTH        : positive := 128; -- Number of characters in SB source element
+  constant C_SB_SLV_WIDTH           : positive :=   8; -- Width of the SLV in the predefined SLV SB
+
+  -- Default message Id panel intended for use in SB
+  constant C_SB_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
+    ID_CTRL => ENABLED,
+    ID_DATA => DISABLED,
+    others  => DISABLED
+  );
+
+end package adaptations_pkg;
+
+package body adaptations_pkg is
+end package body adaptations_pkg;

tb/evr320_decoder_tb.vhd

@@ -0,0 +1,426 @@
+--------------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+--------------------------------------------------------------------------------
+-- Unit    : evr320_decoder_tb.vhd
+-- Author  : Goran Marinkovic, Section Diagnostic, Jonas Purtschert
+-- Version : $Revision: 1.1 $
+--------------------------------------------------------------------------------
+-- Copyright© PSI, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Comment : This is the test bench for the evr component.
+--------------------------------------------------------------------------------
+-- Std. library (platform) -----------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_textio.all;
+use ieee.std_logic_1164.all;
+
+library std;
+use std.env.all;
+use std.textio.all;
+
+library uvvm_util;
+context uvvm_util.uvvm_util_context;
+
+-- Work library (application) --------------------------------------------------
+library work;
+use work.evr320_pkg.all;
+
+entity evr320_decoder_tb is
+end entity;
+
+architecture testbench of evr320_decoder_tb is
+
+   ---------------------------------------------------------------------------
+   -- System
+   ---------------------------------------------------------------------------
+   -- System
+   constant C_RXUSRCLK_CYCLE      : time:= 7 ns;
+   constant C_USRCLK_CYCLE        : time:= 8 ns;
+   ---------------------------------------------------------------------------
+   -- MGT stream
+   ---------------------------------------------------------------------------
+   type mgt_stream_sample_type is record
+      data      : std_logic_vector(7 downto  0);
+      data_k    : std_logic_vector(0 downto 0);        
+      event     : std_logic_vector(7 downto  0);
+      event_k   : std_logic_vector(0 downto 0);
+   end record mgt_stream_sample_type;
+
+   type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
+
+   signal mgt_stream_index  : integer range 0 to 511 := 0;
+   signal mgt_stream        : mgt_stream_type(511 downto 0) := (others=>(others=>(others=>'0')));
+   
+   -----------------------------------------------------------------------------
+   -- Timing decoder interface
+   -----------------------------------------------------------------------------
+   -- Link status
+   signal   rxlos                 : std_logic := '0';
+   -- Clock
+   signal   rxusrclk              : std_logic := '0';
+   -- Data
+   signal   rxdata                : std_logic_vector(15 downto  0) := (others => '0');
+   -- Status 8B/10B decoder
+   signal   rxcharisk             : std_logic_vector( 1 downto  0) := (others => '0');
+
+   signal   usr_clk               : std_logic := '0';
+   signal   evr_params            : typ_evr320_params;
+   signal   mem_addr              : std_logic_vector(13 downto  0) := (others => '0');
+   signal   mem_data              : std_logic_vector(31 downto  0) := (others => '0');
+   -- Decoder stream:
+   type dec_stream_type is record
+     data : std_logic_vector(7 downto 0);
+     addr : std_logic_vector(10 downto 0);
+   end record dec_stream_type;
+   type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
+
+   signal   dec_stream_data           : std_logic_vector(7 downto  0) := (others => '0');
+   signal   dec_stream_addr           : std_logic_vector(10 downto  0) := (others => '0');
+   signal   dec_stream_valid          : std_logic;
+   signal   dec_stream_check      : dec_stream_check_arr(0 to 2047);
+   signal   dec_stream_recv_bytes : integer range 0 to 2047;
+
+   type     segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
+   signal   segment_addr          : std_logic_vector(7 downto 0);
+   signal   segment_data          : segment_data_arr(0 to 2047);
+   signal   segment_length        : natural range 0 to 2047;
+  
+   signal   usr_events            : std_logic_vector( 3 downto  0) := (others => '0');
+   
+   constant FILTER_ADDRESS        : std_logic_vector(11 downto 0) := x"028";
+   constant FILTER_NUM_BYTES      : integer := 8;
+   constant STIMULI_RUNS          : integer := 2;
+
+   signal   received_events       : integer := 0;
+   signal   expect_num_events     : integer := 0;
+   signal   filter_data, filter_data_check : std_logic_vector(63 downto  0) := (others => '0');
+   signal   filter_valid          : std_logic := '0';
+
+begin
+
+   -----------------------------------------------------------------------------
+   -- Timing decoder
+   -----------------------------------------------------------------------------
+   evr320_decoder_inst: entity work.evr320_decoder
+   port map
+   (
+      --------------------------------------------------------------------------
+      -- Debug interface
+      --------------------------------------------------------------------------
+      debug_clk                   => open,
+      debug                       => open,
+      --------------------------------------------------------------------------
+      -- GTX parallel interface
+      --------------------------------------------------------------------------
+      i_mgt_rst                   => rxlos,
+      i_mgt_rx_clk                => rxusrclk,
+      i_mgt_rx_data               => rxdata,
+      i_mgt_rx_charisk            => rxcharisk,
+      --------------------------------------------------------------------------
+      -- User interface CPU clock
+      --------------------------------------------------------------------------
+      i_usr_clk                   => usr_clk,
+      i_evr_params                => evr_params,
+      o_event_recorder_stat       => open,
+      i_event_recorder_ctrl       => c_INIT_EVT_REC_CTRL,
+      i_mem_addr                  => mem_addr,
+      o_mem_data                  => mem_data,
+      --------------------------------------------------------------------------
+      -- User stream interface User clock
+      --------------------------------------------------------------------------
+      i_stream_clk                => usr_clk,
+      o_stream_data               => dec_stream_data,
+      o_stream_addr               => dec_stream_addr,
+      o_stream_valid              => dec_stream_valid,
+      --------------------------------------------------------------------------
+      -- User interface MGT clock
+      --------------------------------------------------------------------------
+      o_usr_events                => usr_events,
+      o_usr_events_ext            => open,
+      o_sos_event                 => open
+   );
+
+    evr320_data_filter_inst: entity work.evr320_data_filter
+    generic map (
+      ADDRESS   => FILTER_ADDRESS,
+      NUM_BYTES => 8
+    )
+    port map (
+      i_stream_clk   => usr_clk,
+      i_stream_data  => dec_stream_data,
+      i_stream_addr  => dec_stream_addr,
+      i_stream_valid => dec_stream_valid,
+      o_data         => filter_data,
+      o_valid        => filter_valid
+    );
+   -----------------------------------------------------------------------------
+   -- MGT / User clock
+   -----------------------------------------------------------------------------
+   clock_generator(rxusrclk, C_RXUSRCLK_CYCLE);  
+   clock_generator(usr_clk, C_USRCLK_CYCLE);  
+
+   -----------------------------------------------------------------------------
+   -- Decoder reset due to MGT main status
+   -----------------------------------------------------------------------------
+   process
+   begin
+      rxlos                       <= '1';
+      wait for 50 ns;
+      wait until (falling_edge(rxusrclk));
+      rxlos                       <= '0';
+      wait ;
+   end process;
+
+    ---------------------------------------------------------
+    -- Receive decoder data stream
+    ---------------------------------------------------------
+    process
+      variable addr : std_logic_vector(10 downto 0);
+      variable data : std_logic_vector(7 downto 0);
+      variable i : integer := 0;
+    begin
+       wait until rising_edge(usr_clk);
+       if (dec_stream_valid = '1') then
+         addr := dec_stream_addr;
+         data := dec_stream_data;
+         i :=  to_integer(unsigned(addr)) -  to_integer(unsigned(segment_addr))*16;
+         -- save stream for later comparision:
+         dec_stream_check(i).addr <= addr;
+         dec_stream_check(i).data <= data;
+         log(ID_SEGMENT_DATA, "Recv Decoder Stream: count=" & integer'image(i) & " addr=0x" & to_string(addr, HEX) & " data=0x" & to_string(data, HEX));
+         i := i + 1;
+         dec_stream_recv_bytes <= i;
+       end if;
+    end process;
+
+    ---------------------------------------------------------
+    -- Wait for Event
+    ---------------------------------------------------------
+    process
+    begin
+      wait until rising_edge(usr_clk);
+      for i in 0 to 3 loop
+        if (usr_events(i) = '1') then
+          log(ID_CTRL, "Event Received: 0x" & to_string(evr_params.event_numbers(i), HEX) );
+          received_events <= received_events + 1;
+        end if;
+      end loop;
+    end process;
+
+    ---------------------------------------------------------
+    -- Fetch filter data
+    ---------------------------------------------------------
+    process
+    begin
+       wait until rising_edge(usr_clk);
+       if (filter_valid = '1') then
+         filter_data_check <= filter_data;
+         log(ID_SEGMENT_DATA, "Filter Valid: data=0x" & to_string(filter_data, HEX));
+       end if;
+    end process;
+
+    -----------------------------------------------------------------------------
+    -- Read stimuli file
+    -----------------------------------------------------------------------------
+    file_blk : block
+      file file_stimuli : text;
+      type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done);
+    begin
+      process
+        variable file_line : line;
+        variable data, event : std_logic_vector(7 downto 0);
+        variable data_k, event_k : std_logic_vector(0 downto 0);
+        variable space : character;
+        variable i : integer;
+        variable parse_fsm : parse_fsm_state := idle;
+        variable payload_cnt : integer range 0 to 2047;
+        variable event_cnt : integer := 0;
+      begin
+        file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode);
+        readline(file_stimuli, file_line); -- comment
+        readline(file_stimuli, file_line); -- comment
+        i := 0;
+        -- read line by line from .dat file:
+        while not endfile(file_stimuli) loop
+          readline(file_stimuli, file_line);
+          hread(file_line, event);
+          read(file_line, event_k);
+          read(file_line, space);
+          read(file_line, space);
+          hread(file_line, data);
+          read(file_line, space);
+          read(file_line, data_k);
+          -- write to array:
+          mgt_stream(i).data <= data;
+          mgt_stream(i).data_k <= data_k;
+          mgt_stream(i).event <= event;
+          mgt_stream(i).event_k <= event_k;
+          mgt_stream_index <= i; 
+          --debug output:
+          --log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) &  "  event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX) 
+          --                                         & "  data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & "  ");
+          -- Count Events:
+          ----------------
+          if (event /= x"00" and event_k = "0") then
+            event_cnt := event_cnt + 1;
+          end if;
+          expect_num_events <= event_cnt * STIMULI_RUNS;
+
+          -- Parse only segment:
+          ----------------------
+          case (parse_fsm) is
+            when idle =>
+              if (data = x"5C" and data_k = "1") then -- check if frame start
+                parse_fsm := seg_start;
+              end if;
+            when seg_start => 
+              parse_fsm := seg_addr;
+            when seg_addr =>
+              segment_addr <= data;
+              parse_fsm := seg_wait;
+            when seg_wait =>
+              parse_fsm := seg_payload;
+              payload_cnt := 0;
+            when seg_payload =>
+              if (data = x"3C" and data_k = "1") then -- check if frame end
+                parse_fsm := seg_done;
+              else
+                segment_data(payload_cnt) <= data;
+                parse_fsm := seg_payload_wait;
+                segment_length <= payload_cnt+1;
+              end if;
+            when seg_payload_wait =>
+              payload_cnt := payload_cnt + 1;
+              parse_fsm := seg_payload;
+            when seg_done =>
+              -- done
+          end case;
+          i := i + 1;
+        end loop;
+        file_close(file_stimuli);
+        wait;
+      end process;
+    end block;
+
+   -----------------------------------------------------------------------------
+   -- Stimulus CPU interface
+   -----------------------------------------------------------------------------
+   process
+      constant C_SCOPE     : string  := C_TB_SCOPE_DEFAULT;    
+      constant c_TB_NAME   : string  := "evr320_decoder_tb";
+      variable mgt_stream_rep_var                    : integer := 0;
+      variable mgt_stream_index_var                  : integer := 0;
+      variable i : integer := 0;
+      type state is (idle, payload, frame_end, segment_nr);
+      variable mem_base : integer range 0 to 127;
+      variable segment_data_word : std_logic_vector(31 downto 0);
+      variable var_filter_offset : integer range 0 to 2047;
+      variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0);
+   begin
+    -- init uvvm:
+    set_log_file_name(c_TB_NAME & "_LOG.txt");
+    set_alert_file_name(c_TB_NAME & "_ALERT.txt");
+    set_alert_stop_limit(ERROR, 0);   -- never(0) pause simulator on error
+    set_alert_stop_limit(TB_ERROR, 0);   -- never(0) pause simulator on error
+    enable_log_msg(ALL_MESSAGES); 
+    log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE);
+
+    --------------------------------------------------------------------------
+    -- Get out of reset, enable events
+    --------------------------------------------------------------------------
+    evr_params.event_enable( 0) <= '1';
+    evr_params.event_enable( 1) <= '0';
+    evr_params.event_enable( 2) <= '0';
+    evr_params.event_enable( 3) <= '0';
+    evr_params.event_numbers( 0)<= X"0F";
+    evr_params.event_numbers( 1)<= X"00";
+    evr_params.event_numbers( 2)<= X"00";
+    evr_params.event_numbers( 3)<= X"00";
+    evr_params.cs_min_cnt  <= X"00000000";
+    evr_params.cs_min_time <= X"00000000";
+    mem_addr <= (others=>'0');
+    await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
+    --wait until (rxlos = '0');
+
+    --------------------------------------------------------------------------
+    -- Stimuli MGT
+    --------------------------------------------------------------------------
+    wait until rising_edge(rxusrclk);
+    for b in 0 to STIMULI_RUNS-1 loop
+      log(ID_DATA, "Send stimuli stream to MGT");
+      for idx in 0 to mgt_stream_index loop
+        --log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX));
+        wait until rising_edge(rxusrclk);
+        rxdata <= mgt_stream(idx).data & mgt_stream(idx).event;
+        rxcharisk <= mgt_stream(idx).data_k & mgt_stream(idx).event_k;
+      end loop;
+    end loop;
+
+    --------------------------------------------------------------------------
+    -- Check if decoder stream is correct
+    --------------------------------------------------------------------------
+    await_value(dec_stream_recv_bytes, segment_length, 0 ns, 5 us, ERROR, "Wait for right number of bytes streamed");
+    -- loop through segment and compare frame bytes with received decoder-stream:
+    for idx in 0 to segment_length-1 loop
+        check_value(dec_stream_check(idx).data, segment_data(idx), ERROR, "Compare Sent and Received Decoder Stream Data");
+    end loop;
+
+    --------------------------------------------------------------------------
+    -- Check if filter data is correct
+    --------------------------------------------------------------------------
+    var_filter_offset := to_integer(unsigned(FILTER_ADDRESS)) - (to_integer(unsigned(segment_addr))*16);
+    --log(ID_CTRL, "var_filter_offset=" & integer'image(var_filter_offset) & " : " & to_string(FILTER_ADDRESS,HEX) & " : " & to_string(segment_addr, HEX)); 
+    for idx in 0 to FILTER_NUM_BYTES-1 loop
+      var_filter_word := var_filter_word(var_filter_word'high-8 downto 0) & segment_data(var_filter_offset + idx); 
+    end loop;
+    check_value(filter_data_check, var_filter_word, ERROR, "Check Data Stream Filter " 
+                                                            & "addr=0x" & to_string(FILTER_ADDRESS, HEX)
+                                                            & " bytes=" & integer'image(FILTER_NUM_BYTES));
+
+    --------------------------------------------------------------------------
+    -- Check if correct number of events has been detected
+    --------------------------------------------------------------------------
+    check_value(received_events, expect_num_events, ERROR, "Check correct number of received events"); 
+
+    --------------------------------------------------------------------------
+    -- Read DPRAM buffer
+    --------------------------------------------------------------------------
+    wait for 1 us;
+    log(ID_DATA, "Read Segment from DPRAM");
+    -- print 16 words from dpram data buffer:
+    for offset in 0 to segment_length/4-1 loop
+      mem_base := to_integer(unsigned(segment_addr));
+      mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 14));
+      wait until rising_edge(usr_clk);
+      wait until rising_edge(usr_clk);
+      wait until rising_edge(usr_clk);
+      segment_data_word := segment_data(offset*4+3) 
+                            & segment_data(offset*4+2) 
+                            & segment_data(offset*4+1) 
+                            & segment_data(offset*4);
+      check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment");
+      --log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX));
+    end loop;
+
+    --------------------------------------------------------------------------
+    -- Test Done
+    --------------------------------------------------------------------------
+    log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
+    report_alert_counters(VOID);
+
+     assert shared_uvvm_status.found_unexpected_simulation_warnings_or_worse = 0 
+       report "UVVM Found unexpected warnings or worse" severity ERROR;
+     
+       stop(0); 
+      -- finish(0); -- wants to close modelsim!?
+      wait;
+   end process;
+
+end architecture testbench;
+
+--------------------------------------------------------------------------------
+-- End of file
+--------------------------------------------------------------------------------

tb/stimuli_mgt.dat

@@ -0,0 +1,131 @@
+# stimuli timing master frame, hex
+# event k data k comment
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  5C 1   frame start
+00 0  00 0   gap
+00 0  02 0   frame byte
+BC 1  00 0   align
+00 0  DB 0   frame byte
+00 0  00 0   gap
+00 0  93 0   frame byte
+BC 1  00 0   align
+00 0  36 0   frame byte
+00 0  00 0   gap
+00 0  41 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  A3 0   frame byte
+00 0  00 0   gap
+00 0  1D 0   frame byte
+BC 1  00 0   align
+00 0  7F 0   frame byte
+00 0  00 0   gap
+00 0  33 0   frame byte
+BC 1  00 0   align
+00 0  9B 0   frame byte
+00 0  00 0   gap
+00 0  F3 0   frame byte
+BC 1  00 0   align
+00 0  51 0   frame byte
+00 0  00 0   gap
+00 0  04 0   frame byte
+BC 1  00 0   align
+00 0  6B 0   frame byte
+00 0  00 0   gap
+00 0  7C 0   frame byte
+BC 1  00 0   align
+00 0  16 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  00 0   frame byte
+00 0  00 0   gap
+00 0  00 0   frame byte
+BC 1  00 0   align
+00 0  3C 1   frame end
+00 0  00 0   gap
+00 0  F9 0   check sum MSB
+BC 1  00 0   align
+00 0  C6 0   check sum LSB
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+00 0  00 0   gap
+00 0  00 0   gap
+BC 1  00 0   align
+00 0  00 0   gap
+0F 0  00 0   BPM event
+00 0  00 0   gap