AEK_8220_Libraries/firmware_vhdl_evr320
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new address map, changed recorder and segment memory

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This commit is contained in:
purtschert_j
2019-02-17 22:26:17 +01:00
parent 1e554877ad
commit 05ae75f812
8 changed files with 33847 additions and 28928 deletions
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5
Changelog.md
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@ -1,3 +1,8 @@
## 3.0
* Added Simulation
* Added Decoder streaming output
* Changed Register and Memory Address Map
## 2.2
* Added Features

62719
doc/evr320.rtf
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doc/evr320.vsd
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doc/evr_register_mapping.xlsx Normal file
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24
hdl/evr320_decoder.vhd
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@ -48,7 +48,7 @@ entity evr320_decoder is
i_evr_params : in typ_evr320_params;
o_event_recorder_stat : out typ_evt_rec_status;
i_event_recorder_ctrl : in typ_evt_rec_ctrl;
i_mem_addr : in std_logic_vector(11 downto 0);
i_mem_addr : in std_logic_vector(13 downto 0);
o_mem_data : out std_logic_vector(MEM_DATA_WIDTH - 1 downto 0);
--------------------------------------------------------------------------
-- User stream interface User clock
@ -172,7 +172,7 @@ architecture behavioral of evr320_decoder is
constant mem_ctrl_rd : std_logic_vector( 1 downto 0) := "11";
signal mem_fsm : std_logic_vector( 1 downto 0) := "00";
-- Data memory address
signal mem_addr : std_logic_vector(11 downto 0);
signal mem_addr : std_logic_vector(13 downto 0);
-- Data memory write
signal mem_data_wren : std_logic := '0';
signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
@ -268,7 +268,7 @@ begin
-- Address Alignment for 32/64-bit Data Width
-----------------------------------------------------------------------------
gen_addr_align64: if MEM_DATA_WIDTH = 64 generate
mem_addr <= i_mem_addr(10 downto 0) & '0';
mem_addr <= i_mem_addr(12 downto 0) & '0';
end generate gen_addr_align64;
gen_addr_align32: if MEM_DATA_WIDTH = 32 generate
@ -703,8 +703,12 @@ begin
-----------------------------------------------------------------------------
-- Data memory selector
-----------------------------------------------------------------------------
o_mem_data <= mem_data_dpram when (mem_addr(11 downto 9) = "000") else
mem_data_event_recorder;
-- Memory Map (byte-address):
-- * Segmented Data Buffer: 0x9000 - 0x97FF
-- * Event Recorder: 0xB000 - 0xBFFF
o_mem_data <= mem_data_dpram when (mem_addr(13 downto 9) = "10010") else
mem_data_event_recorder when (mem_addr(13 downto 10) = "1011") else
x"DEADC0DE";
-----------------------------------------------------------------------------
-- Data Memory
@ -923,11 +927,11 @@ begin
--------------------------------------------------------------------------
-- Memory Selector Event Recorder
--------------------------------------------------------------------------
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr(11 downto 9) = B"101") else -- 2K
mem_data_event_nr_timestamp when (mem_addr(11 downto 8) = B"1100") else -- 1K
mem_data_segment_timestamp when (mem_addr(11 downto 7) = B"1101_0") else -- 512B
mem_data_event_nr when (mem_addr(11 downto 6) = B"1101_10") else -- 256B
mem_data_event_flag when (mem_addr(11 downto 6) = B"1101_11") else -- 256B
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr(13 downto 9) = B"1011_0") else -- 2K
mem_data_event_nr_timestamp when (mem_addr(13 downto 8) = B"1011_10") else -- 1K
mem_data_segment_timestamp when (mem_addr(13 downto 7) = B"1011_110") else -- 512B
mem_data_event_nr when (mem_addr(13 downto 6) = B"1011_1110") else -- 256B
mem_data_event_flag when (mem_addr(13 downto 6) = B"1011_1111") else -- 256B
(others => '0');

6
hdl/evr320_ifc1210_wrapper.vhd
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@ -41,7 +41,7 @@ entity evr320_ifc1210_wrapper is
xuser_RESET: in std_logic;
xuser_TMEM_ENA: in std_logic;
xuser_TMEM_WE: in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD: in std_logic_vector(13 downto 3);
xuser_TMEM_ADD: in std_logic_vector(15 downto 3);
xuser_TMEM_DATW: in std_logic_vector(63 downto 0);
xuser_TMEM_DATR: out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------
@ -99,8 +99,8 @@ architecture rtl of evr320_ifc1210_wrapper is
signal mgt_reset_tmem_evr : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
signal mem_clk : std_logic;
signal mem_addr_evr : std_logic_vector(11 downto 0);
signal mem_addr_tosca : std_logic_vector(10 downto 0);
signal mem_addr_evr : std_logic_vector(13 downto 0);
signal mem_addr_tosca : std_logic_vector(12 downto 0);
signal mem_data : std_logic_vector(c_TOSCA2_DATA_WIDTH-1 downto 0);
signal evr_params : typ_evr320_params;

15
hdl/evr320_tmem.vhd
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@ -29,7 +29,7 @@ entity evr320_tmem is
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_ADD : in std_logic_vector(15 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
---------------------------------------------------------------------------
@ -42,7 +42,7 @@ entity evr320_tmem is
mgt_status_i : in std_logic_vector(31 downto 0);
mgt_reset_o : out std_logic;
mem_clk_o : out std_logic;
mem_addr_o : out std_logic_vector(10 downto 0);
mem_addr_o : out std_logic_vector(12 downto 0);
mem_data_i : in std_logic_vector(63 downto 0)
);
end evr320_tmem;
@ -58,7 +58,6 @@ architecture rtl of evr320_tmem is
constant TMEM_ADDR_LSB : integer := 3; -- 64 bit
constant REG_ADDR_WIDTH : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
constant REG_ADDR_MSB : integer := REG_ADDR_WIDTH - 1;
constant MEM_ADDR_START : std_logic_vector(7 downto 0) := X"10";
@ -68,7 +67,7 @@ architecture rtl of evr320_tmem is
-- xuser tmem signals
signal xuser_TMEM_WE_reg : std_logic_vector( 7 downto 0) := (others => '0');
signal xuser_TMEM_ENA_reg : std_logic := '0';
signal xuser_TMEM_ADD_reg : std_logic_vector(13 downto 3) := (others => '0');
signal xuser_TMEM_ADD_reg : std_logic_vector(15 downto 3) := (others => '0');
signal xuser_TMEM_DATW_reg : std_logic_vector(63 downto 0) := (others => '0');
-- evr params
@ -146,7 +145,7 @@ begin
begin
if (rising_edge(xuser_CLK)) then
if (xuser_TMEM_ENA_reg = '1') then
if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0) then
if (xuser_TMEM_ADD_reg(15 downto REG_ADDR_WIDTH) = 0) then
case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
@ -180,7 +179,7 @@ begin
er_error_ack <= er_error_ack(2 downto 0) & '0';
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0) then
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(15 downto REG_ADDR_WIDTH) = 0) then
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
-- if xuser_TMEM_WE_reg(0) = '1' then -read only- <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
@ -246,7 +245,7 @@ begin
-- Port mapping
-- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK;
mem_addr_o <= xuser_TMEM_ADD - MEM_ADDR_START;
mem_addr_o <= xuser_TMEM_ADD;
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
@ -256,4 +255,4 @@ begin
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------

6
tb/evr320_decoder_tb.vhd
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@ -68,7 +68,7 @@ architecture testbench of evr320_decoder_tb is
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_addr : std_logic_vector(13 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-- Decoder stream:
type dec_stream_type is record
@ -341,7 +341,7 @@ begin
evr_params.event_numbers( 3)<= X"00";
evr_params.cs_min_cnt <= X"00000000";
evr_params.cs_min_time <= X"00000000";
mem_addr <= x"000";
mem_addr <= (others=>'0');
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
--wait until (rxlos = '0');
@ -393,7 +393,7 @@ begin
-- print 16 words from dpram data buffer:
for offset in 0 to segment_length/4-1 loop
mem_base := to_integer(unsigned(segment_addr));
mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 14));
wait until rising_edge(usr_clk);
wait until rising_edge(usr_clk);
wait until rising_edge(usr_clk);