Commit Graph

487 Commits

Author SHA1 Message Date
e4ac3e8b08 FPGASpotFindingUnitTest: Very basic test for spot finder 2023-10-18 12:10:29 +02:00
6565619035 parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS) 2023-10-18 12:10:00 +02:00
79df7cf7d5 FPGA: Add extra AXI-Stream register slices 2023-10-17 19:40:55 +02:00
83fb1fd465 FPGA: Clean-up of prefix_sum 2023-10-17 13:22:49 +02:00
217992be94 FPGA: Second variant of prefix sum 2023-10-17 10:39:11 +02:00
05338887a7 FPGA: Spot finder accepts 16-bit number for strong pixel threshold 2023-10-16 22:07:41 +02:00
faca7a3f15 PCIe driver: Clean-up + add intermediate library between driver and AcquisitionDevice 2023-10-16 19:54:13 +02:00
2fd8d38782 PCIe driver: add basic permission handling 2023-10-16 15:13:47 +02:00
202b7ee0ca PCIe driver: clean-up 2023-10-16 15:13:47 +02:00
c5ca10792e FPGA: Clean-up of spot_finder core + update README.MD 2023-10-16 15:13:47 +02:00
9b646a4195 FPGA: Spot finder 2nd version more improved 2023-10-04 16:59:13 +02:00
7889f1666a FPGA: Spot finder 2nd version improved 2023-10-04 12:12:43 +02:00
5460c10f76 FPGA: Spot finder 2nd version 2023-10-03 22:14:11 +02:00
81c1502d52 FPGA: Added spot_finder_line_sum (work in progress) 2023-10-03 18:51:26 +02:00
f301923c72 FPGA: Added spot_finder_update_sum function, as first step for versatile spot finder 2023-10-03 14:28:39 +02:00
c6afbebd13 FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result) 2023-10-02 22:34:49 +02:00
98fe70315b FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design) 2023-09-30 11:28:01 +02:00
59d0850b1f FPGA: integration results are reduced to cover two bins per 512-bit 2023-09-29 22:08:55 +02:00
ca118f26d5 FPGA: integration results are reduced to cover two bins per 512-bit 2023-09-29 22:07:52 +02:00
8831ad380f FPGA: Fix bug in adu_histo + add test + add access from AcquisitionDevice 2023-09-29 18:34:29 +02:00
549cc6a887 FPGA: Add ADU histogram (work in progress; needs test) 2023-09-29 16:55:37 +02:00
5bb92aed61 FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer 2023-09-29 14:44:08 +02:00
79aef71ce3 FPGA: spot_finder added 2023-09-26 18:54:31 +02:00
84bf69b8a6 FPGA: frame generator reads from HBM (work in progress) 2023-09-26 13:14:43 +02:00
0f7c14c267 FPGA: integration calculates sum^2 2023-09-25 22:23:06 +02:00
7e3b9cfeba Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
2023-09-25 21:52:55 +02:00
027b3aa943 Revert "FPGA: add register slices"
This reverts commit cf2163a402.
2023-09-25 21:52:54 +02:00
4028a59c4a PCIe driver: add option to read/write register 2023-09-24 22:58:16 +02:00
556c4c4aec PCIe driver: move include for common/Definitions.h 2023-09-24 22:46:50 +02:00
cf2163a402 FPGA: add register slices 2023-09-24 20:28:35 +02:00
df0b0d8b96 FPGA: add spot finder to the design 2023-09-24 19:04:58 +02:00
f4f4b50be7 FPGA: frame_generator has 8 module specific frames 2023-09-24 15:43:04 +02:00
ae6e036628 FPGA: increase frame_generator memory to 8 MiB 2023-09-24 14:39:46 +02:00
4dfc8a1a59 FPGA: spot_finder threshold can be set externally 2023-09-23 15:17:35 +02:00
a70e3cf444 FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis 2023-09-22 21:49:41 +02:00
2cfde3a82d FPGA: spot_finder early work in progress 2023-09-22 20:43:52 +02:00
5cf0d30603 AcquisitionDevice: Enable access to integration results 2023-09-22 20:32:13 +02:00
3f3ce6f354 FPGA: fix integration bug 2023-09-22 20:32:12 +02:00
f06e92fd1b FPGA: load_calibration allows to upload integration map 2023-09-22 18:28:35 +02:00
2c9d623265 integration: use separate FIFO for integration results 2023-09-22 17:49:14 +02:00
bb29e7e646 HLS_C_Simulation_check_single_packet: check for memory content for missed packets 2023-09-21 18:39:05 +02:00
2eb85496f2 FPGA: add integration routine (work in progress) 2023-09-21 17:12:01 +02:00
21bed7ee72 FPGA: host_writer writes module statistics 2023-09-21 13:19:23 +02:00
2a0122393c FPGA: Fix license 2023-09-21 13:10:55 +02:00
a5aed37100 Definitions.h: Increase space for data processing results 2023-09-21 10:08:53 +02:00
ffa3a2cdac FPGAAcquisitionDevice: Put warning for wrong data collection ID 2023-09-20 16:52:59 +02:00
8c1bc9d89d FPGA: Remove non-blocking mode 2023-09-20 16:41:14 +02:00
88e837a33a FPGAAcquisitionDevice: Remove non-blocking mode 2023-09-20 16:29:50 +02:00
6cbd577824 DetectorSetup: Configure UDP interface count 2023-09-20 14:00:10 +02:00
aa3d9e5edb DetectorWrapper: Add warning message when having problem stopping the detector 2023-09-20 11:01:13 +02:00