FPGA: spot_finder threshold can be set externally

This commit is contained in:
2023-09-23 15:17:35 +02:00
parent a70e3cf444
commit 4dfc8a1a59
2 changed files with 7 additions and 7 deletions
+1
View File
@@ -53,6 +53,7 @@ typedef hls::stream<packet_512_t> STREAM_512;
#define ACT_REG_NFRAMES(x) ((x)(95 , 64)) // 32 bit
#define ACT_REG_NMODULES(x) ((x)(132, 128)) // 5 bit (0..31)
#define ACT_REG_NSTORAGE_CELLS(x) ((x)(148, 144)) // 5 bit
#define ACT_REG_SPOT_FINDER_THRESHOLD(x) ((x)(175, 160)) // 16 bit
struct axis_datamover_ctrl {
ap_uint<40+64> data;
+6 -7
View File
@@ -1,7 +1,5 @@
// Copyright (2019-2023) Paul Scherrer Institute
// Copyright (2019-2023) Paul Scherrer Institute
#include "hls_jfjoch.h"
void spot_finder(STREAM_512 &data_in,
@@ -15,6 +13,7 @@ void spot_finder(STREAM_512 &data_in,
packet_512_t packet;
data_in >> packet;
data_out << packet;
ap_int<16> threshold = ACT_REG_SPOT_FINDER_THRESHOLD(packet.data);
ap_uint<32> result[RAW_MODULE_SIZE * sizeof(uint16_t) / 64];
#pragma HLS ARRAY_PARTITION variable=result type=cyclic factor=16
@@ -24,13 +23,13 @@ void spot_finder(STREAM_512 &data_in,
while (!packet.user) {
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
ap_uint<32> output = 0;
data_out << packet;
unpack32(packet.data, val);
for (int j = 0; j < 32; j++) {
if (val[j] > 5)
output[j] = 1;
}
ap_uint<32> output;
for (int j = 0; j < 32; j++)
output[j] = ((val[j] > threshold) ? 1 : 0);
data_in >> packet;
result[i] = output;
}