Commit Graph
95 Commits
Author SHA1 Message Date
leonarski_f e1a6830c50 FPGA: Add multipixel (-> TODO calculate proper number) 2023-10-24 16:43:24 +02:00
leonarski_f 19644a1f5f FPGA: Trigger synthesis 2023-10-21 16:12:51 +02:00
leonarski_f 4ede0f1f15 FPGA: rename axis_256_to_512.cpp file 2023-10-21 15:38:40 +02:00
leonarski_f 3b65e6bf88 FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5) 2023-10-21 15:37:46 +02:00
leonarski_f 7008703af3 FPGA: Integration is not calculating sum2 2023-10-20 14:06:58 +02:00
leonarski_f ad78fb0149 FPGA: Fixes and simplifications to spot_finder core + SNR threshold test 2023-10-20 12:23:50 +02:00
leonarski_f 45de356c16 FPGA: Minor changes 2023-10-19 22:43:35 +02:00
leonarski_f aa1ff0436b FPGA: Add SNR threshold to spot finder 2023-10-19 22:29:38 +02:00
leonarski_f 60466fe146 FPGA: Add extra comment to spot_finder 2023-10-19 20:56:24 +02:00
leonarski_f 9f48e4b317 FPGA: remove spot_finder.h 2023-10-19 20:53:38 +02:00
leonarski_f f04f7a274b FPGA: Name spot finder signals in consistent manner 2023-10-19 20:52:09 +02:00
leonarski_f 90344eb251 FPGA: Basic spot finder (i.e. only based on count threshold) as a placeholder 2023-10-19 19:40:31 +02:00
leonarski_f 6f9f918ee6 HLS: Improve make scripts, so HLS test bench can be defined 2023-10-18 16:32:31 +02:00
leonarski_f 736a181e5e HLS: Spot finder outputs parameters + statistics 2023-10-18 15:19:01 +02:00
leonarski_f ec7278bd44 HLS: Changes to allow cosimulation with Vitis HLS 2023-10-18 14:44:30 +02:00
leonarski_f 6565619035 parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS) 2023-10-18 12:10:00 +02:00
leonarski_f 83fb1fd465 FPGA: Clean-up of prefix_sum 2023-10-17 13:22:49 +02:00
leonarski_f 217992be94 FPGA: Second variant of prefix sum 2023-10-17 10:39:11 +02:00
leonarski_f 05338887a7 FPGA: Spot finder accepts 16-bit number for strong pixel threshold 2023-10-16 22:07:41 +02:00
leonarski_f c5ca10792e FPGA: Clean-up of spot_finder core + update README.MD 2023-10-16 15:13:47 +02:00
leonarski_f 9b646a4195 FPGA: Spot finder 2nd version more improved 2023-10-04 16:59:13 +02:00
leonarski_f 7889f1666a FPGA: Spot finder 2nd version improved 2023-10-04 12:12:43 +02:00
leonarski_f 5460c10f76 FPGA: Spot finder 2nd version 2023-10-03 22:14:11 +02:00
leonarski_f 81c1502d52 FPGA: Added spot_finder_line_sum (work in progress) 2023-10-03 18:51:26 +02:00
leonarski_f f301923c72 FPGA: Added spot_finder_update_sum function, as first step for versatile spot finder 2023-10-03 14:28:39 +02:00
leonarski_f c6afbebd13 FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result) 2023-10-02 22:34:49 +02:00
leonarski_f 98fe70315b FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design) 2023-09-30 11:28:01 +02:00
leonarski_f 59d0850b1f FPGA: integration results are reduced to cover two bins per 512-bit 2023-09-29 22:08:55 +02:00
leonarski_f ca118f26d5 FPGA: integration results are reduced to cover two bins per 512-bit 2023-09-29 22:07:52 +02:00
leonarski_f 8831ad380f FPGA: Fix bug in adu_histo + add test + add access from AcquisitionDevice 2023-09-29 18:34:29 +02:00
leonarski_f 549cc6a887 FPGA: Add ADU histogram (work in progress; needs test) 2023-09-29 16:55:37 +02:00
leonarski_f 5bb92aed61 FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer 2023-09-29 14:44:08 +02:00
leonarski_f 79aef71ce3 FPGA: spot_finder added 2023-09-26 18:54:31 +02:00
leonarski_f 84bf69b8a6 FPGA: frame generator reads from HBM (work in progress) 2023-09-26 13:14:43 +02:00
leonarski_f 0f7c14c267 FPGA: integration calculates sum^2 2023-09-25 22:23:06 +02:00
leonarski_f 7e3b9cfeba Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
2023-09-25 21:52:55 +02:00
leonarski_f df0b0d8b96 FPGA: add spot finder to the design 2023-09-24 19:04:58 +02:00
leonarski_f f4f4b50be7 FPGA: frame_generator has 8 module specific frames 2023-09-24 15:43:04 +02:00
leonarski_f 4dfc8a1a59 FPGA: spot_finder threshold can be set externally 2023-09-23 15:17:35 +02:00
leonarski_f a70e3cf444 FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis 2023-09-22 21:49:41 +02:00
leonarski_f 2cfde3a82d FPGA: spot_finder early work in progress 2023-09-22 20:43:52 +02:00
leonarski_f 3f3ce6f354 FPGA: fix integration bug 2023-09-22 20:32:12 +02:00
leonarski_f f06e92fd1b FPGA: load_calibration allows to upload integration map 2023-09-22 18:28:35 +02:00
leonarski_f 2c9d623265 integration: use separate FIFO for integration results 2023-09-22 17:49:14 +02:00
leonarski_f 2eb85496f2 FPGA: add integration routine (work in progress) 2023-09-21 17:12:01 +02:00
leonarski_f 21bed7ee72 FPGA: host_writer writes module statistics 2023-09-21 13:19:23 +02:00
leonarski_f 2a0122393c FPGA: Fix license 2023-09-21 13:10:55 +02:00
leonarski_f 8c1bc9d89d FPGA: Remove non-blocking mode 2023-09-20 16:41:14 +02:00
leonarski_f 25ce039e92 FPGA: Modifications to host_writer to make it functionally closer to old one 2023-09-19 21:24:37 +02:00
leonarski_f 8e0edab0ee AcquisitionDevice: Count completed descriptors 2023-09-19 12:53:59 +02:00