Commit Graph

73 Commits

Author SHA1 Message Date
9630c06b02 Modifications necessary for the EIGER test 2024-04-18 15:36:52 +02:00
38ed2ed56f Use internal trigger to take pedestal + fix fixedG1 pedestal with SCs 2024-04-13 14:27:37 +02:00
c6d2b5eedf File writer and spot finding improvements 2024-04-08 11:18:50 +02:00
59aacf516d Updates March 2023 2024-03-14 20:26:03 +01:00
d315506633 * Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
2024-03-05 20:41:47 +01:00
babb1a5c8d Fixes after MAX IV experiment 2024-02-05 17:18:16 +01:00
f5f86d9ab6 Modifications in preparation to MAX IV experiment 2024-01-27 21:23:56 +01:00
d82bd13917 Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
2023-12-14 22:39:17 +01:00
1798de247b Extend FPGA functionality 2023-12-09 12:08:39 +01:00
96c47cfd73 FPGAIntegrationTest: Fix test 2023-11-23 16:37:58 +01:00
f778a35e6f DiffractionExperiment: Move internal variables to a C++ structure 2023-11-14 13:17:58 +01:00
4efcdaab74 AcqusitionDevice: Moved to dedicated directory 2023-11-10 11:45:16 +01:00
4bc61de084 AcquisitionDevice no longer depends on ProtoBuf (at least directly) 2023-11-08 21:51:42 +01:00
a4af0b380c FPGAIntegrationTest: Fix excesive test output 2023-11-07 19:18:25 +01:00
41985b6c29 FPGA: Increase data width of conversion to 18-bit. This allows to use full unsigned precision + raw data are handled properly. 2023-11-07 19:11:37 +01:00
591e724cf6 DiffractionExperiment: Rename GetFPGAOutputDepth -> GetPixelDepth and GetFPGASummation -> GetSummation 2023-11-06 18:01:53 +01:00
b2743072e6 DiffractionExperiment: Remove frame summation (summation only on FPGA) 2023-11-06 16:09:08 +01:00
3d7c7b0779 Implement FPGA summation 2023-11-02 20:41:37 +01:00
b3eceef7cd FPGA: Max module number is 32 2023-11-01 15:55:06 +01:00
112a62fc7f FPGA: remove limit of modules for frame_generator 2023-11-01 14:20:43 +01:00
a71121482e FPGAIntegrationTest: More parameters in packet generator custom frame test 2023-11-01 13:29:06 +01:00
2ed91c1849 FPGA: transfer for image and processing results are separate DMA transactions 2023-10-28 16:47:06 +02:00
c896ec5659 FPGA: Remove bitshuffle from the pipeline 2023-10-27 19:41:02 +02:00
3b802effa8 HLSSimulatedDevice: Remove module_upside_down 2023-10-27 15:28:49 +02:00
2268486824 HLS: Added frame_summation core 2023-10-26 22:31:09 +02:00
efac89f89e FPGAIntegrationTest: Add invert and bitshuffle tests 2023-10-25 22:37:25 +02:00
c1469d1e46 JFJochReceiver: Skip frames if acquisition finished and frames stopped earlier on the first acquisition device 2023-10-22 14:36:53 +02:00
3b65e6bf88 FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5) 2023-10-21 15:37:46 +02:00
d91eb6bdd5 FPGAIntegrationTest: Use multiple modules 2023-10-21 11:08:07 +02:00
7008703af3 FPGA: Integration is not calculating sum2 2023-10-20 14:06:58 +02:00
ad78fb0149 FPGA: Fixes and simplifications to spot_finder core + SNR threshold test 2023-10-20 12:23:50 +02:00
f04f7a274b FPGA: Name spot finder signals in consistent manner 2023-10-19 20:52:09 +02:00
67b9e08a5c FPGAIntegrationTest: Add test for spot finder based on count limit 2023-10-19 19:48:40 +02:00
a56a54c72d AcquisitionDevice: GetDeviceOutput to get the whole package 2023-10-18 19:42:57 +02:00
faca7a3f15 PCIe driver: Clean-up + add intermediate library between driver and AcquisitionDevice 2023-10-16 19:54:13 +02:00
8831ad380f FPGA: Fix bug in adu_histo + add test + add access from AcquisitionDevice 2023-09-29 18:34:29 +02:00
84bf69b8a6 FPGA: frame generator reads from HBM (work in progress) 2023-09-26 13:14:43 +02:00
0f7c14c267 FPGA: integration calculates sum^2 2023-09-25 22:23:06 +02:00
a70e3cf444 FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis 2023-09-22 21:49:41 +02:00
5cf0d30603 AcquisitionDevice: Enable access to integration results 2023-09-22 20:32:13 +02:00
bb29e7e646 HLS_C_Simulation_check_single_packet: check for memory content for missed packets 2023-09-21 18:39:05 +02:00
88e837a33a FPGAAcquisitionDevice: Remove non-blocking mode 2023-09-20 16:29:50 +02:00
8e0edab0ee AcquisitionDevice: Count completed descriptors 2023-09-19 12:53:59 +02:00
16bbf54f2a Remove open source license (for now) 2023-09-15 10:47:21 +02:00
7a026b89d0 FPGAIntegrationTest: Use blocking mode for one remaining test 2023-09-14 23:48:02 +02:00
0b95456d3d Adapt PCIe driver and tests for the new frame generator 2023-09-13 21:44:20 +02:00
496d016c31 FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets) 2023-09-13 20:06:09 +02:00
9d01630cfc FPGA: load calibration works as dedicated function of the card 2023-09-12 14:34:42 +02:00
05000bab1f FPGA: remove transfer to HBM for the time being 2023-09-11 20:24:20 +02:00
309dabd32b FPGA: Use dedicated struct for address exchange 2023-09-11 11:19:05 +02:00