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FPGAIntegrationTest: Fix test

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This commit is contained in:
leonarski_f
2023-11-23 16:37:58 +01:00
parent 5e7868d17d
commit 96c47cfd73
1 changed files with 3 additions and 7 deletions
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10
tests/FPGAIntegrationTest.cpp
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@@ -946,7 +946,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
act_reg.nsummation);
REQUIRE(idle_data_collection == 0);
REQUIRE(addr1.size() == 1);
REQUIRE(raw1.size() == 1);
// state = INIT
@@ -964,7 +963,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
act_reg.nsummation);
REQUIRE(idle_data_collection == 0);
REQUIRE(addr1.size() == 1);
REQUIRE(raw1.size() == 1);
// state = INIT
@@ -984,7 +982,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
act_reg.nsummation);
REQUIRE(idle_data_collection == 0);
REQUIRE(addr1.size() == 1);
REQUIRE(raw1.size() == 1);
// state = LAST
@@ -1002,7 +999,7 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
act_reg.nsummation);
REQUIRE(idle_data_collection == 0);
REQUIRE(addr1.size() == 2);
REQUIRE(addr1.size() == 1);
REQUIRE(raw1.size() == 2);
// state = WAIT_FOR_START
@@ -1020,7 +1017,7 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
act_reg.nsummation);
REQUIRE(idle_data_collection == 1);
REQUIRE(addr1.size() == 2);
REQUIRE(addr1.size() == 1);
REQUIRE(raw1.size() == 2);
auto packet = raw1.read();
@@ -1030,9 +1027,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
packet = raw1.read();
REQUIRE(packet.last);
REQUIRE(packet.dest == 0);
auto addr = addr1.read();
addr = addr1.read();
auto addr = addr1.read();
REQUIRE(addr.last);
}