diff --git a/tests/FPGAIntegrationTest.cpp b/tests/FPGAIntegrationTest.cpp
index 681777da..8622c2bd 100644
--- a/tests/FPGAIntegrationTest.cpp
+++ b/tests/FPGAIntegrationTest.cpp
@@ -946,7 +946,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
                         act_reg.nsummation);
 
     REQUIRE(idle_data_collection == 0);
-    REQUIRE(addr1.size() == 1);
     REQUIRE(raw1.size() == 1);
 
     // state = INIT
@@ -964,7 +963,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
                         act_reg.nsummation);
 
     REQUIRE(idle_data_collection == 0);
-    REQUIRE(addr1.size() == 1);
     REQUIRE(raw1.size() == 1);
 
     // state = INIT
@@ -984,7 +982,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
                         act_reg.nsummation);
 
     REQUIRE(idle_data_collection == 0);
-    REQUIRE(addr1.size() == 1);
     REQUIRE(raw1.size() == 1);
 
     // state = LAST
@@ -1002,7 +999,7 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
                         act_reg.nsummation);
 
     REQUIRE(idle_data_collection == 0);
-    REQUIRE(addr1.size() == 2);
+    REQUIRE(addr1.size() == 1);
     REQUIRE(raw1.size() == 2);
 
     // state = WAIT_FOR_START
@@ -1020,7 +1017,7 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
                         act_reg.nsummation);
 
     REQUIRE(idle_data_collection == 1);
-    REQUIRE(addr1.size() == 2);
+    REQUIRE(addr1.size() == 1);
     REQUIRE(raw1.size() == 2);
 
     auto packet = raw1.read();
@@ -1030,9 +1027,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
     packet = raw1.read();
     REQUIRE(packet.last);
     REQUIRE(packet.dest == 0);
-    auto addr = addr1.read();
 
-    addr = addr1.read();
+    auto addr = addr1.read();
     REQUIRE(addr.last);
 }