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35aa21fefe
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FPGA: Increase FIFO size to improve buffering capability
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2023-09-07 12:23:38 +02:00 |
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dd002e3d6d
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FPGA: Build only 100G solution (no bifurcated design)
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2023-09-07 12:10:38 +02:00 |
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a6377239cf
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FPGA: fix script for 2x100G design
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2023-09-06 19:07:20 +02:00 |
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0434207882
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FPGA: use full AXI for internal packet generator
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2023-09-06 18:16:44 +02:00 |
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caf950f99f
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FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
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2023-09-06 08:19:03 +02:00 |
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2a0e4b7d4a
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FPGA: Use 200 Hz for 100 Gbit/s design
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2023-08-15 17:31:05 +02:00 |
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f66fc95ecc
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FPGA: Use 250 Hz for 100 Gbit/s design + adjust TCL scripts
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2023-08-15 14:39:04 +02:00 |
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ad5030334a
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FPGA: Add 1 stream design
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2023-08-14 21:55:27 +02:00 |
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3e406f0f46
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FPGA: URAM read latency reduced to 2
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2023-08-12 12:05:53 +02:00 |
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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