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Code Issues Pull Requests Actions Packages Projects Releases 67 Wiki Activity
1,323 Commits 89 Branches 152 Tags
2c51e00aae162eb17ba239683bd89e24a3dd9be3
Commit Graph
76 Commits
Author SHA1 Message Date
leonarski_f 061152279c v1.0.0-rc.91 2025-10-20 20:43:44 +02:00
leonarski_f c67337cfe1 v1.0.0-rc.72 2025-09-08 20:28:59 +02:00
leonarski_f b0607ab3ca v1.0.0-rc.34 2025-04-14 11:52:06 +02:00
leonarski_f ddf4c75645 v1.0.0-rc.31 2025-03-02 13:15:28 +01:00
leonarski_f 28d224afab version 1.0.0-rc.25 2024-11-22 21:25:20 +01:00
leonarski_f adc13ff33e version 1.0.0-rc.24 2024-11-17 14:55:09 +01:00
leonarski_f 40c1e3d49f version 1.0.0-rc.20 2024-10-21 13:30:56 +02:00
leonarski_f 3be959f272 version 1.0.0-rc.14 2024-10-07 11:56:40 +02:00
leonarski_f e812918e2e version 1.0.0-rc.13 2024-10-05 13:14:49 +02:00
leonarski_f 6b5fddf2b7 Version 1.0.0-rc.12 2024-07-06 09:34:44 +02:00
leonarski_f d315506633 * Enhancements for XFEL 
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
 2024-03-05 20:41:47 +01:00
leonarski_f babb1a5c8d Fixes after MAX IV experiment 2024-02-05 17:18:16 +01:00
leonarski_f 6e85a30930 FPGA: Change FIFO size to improve placing 2024-01-28 20:11:39 +01:00
leonarski_f f5f86d9ab6 Modifications in preparation to MAX IV experiment 2024-01-27 21:23:56 +01:00
leonarski_f d82bd13917 Minor fixes for CI and dependencies 
Improvements in documentation and readability of JungfraujochDevice function
 2023-12-14 22:39:17 +01:00
leonarski_f 1798de247b Extend FPGA functionality 2023-12-09 12:08:39 +01:00
leonarski_f a7c2849a84 FPGA: measure pipeline beats in timer 2023-11-21 15:55:23 +01:00
leonarski_f 39ca47aea9 FPGA: Add processing stalls 2023-11-21 15:42:26 +01:00
leonarski_f ba70aa1915 FPGA: Load calibration issues datamover commands first 2023-11-18 22:44:37 +01:00
leonarski_f 08c2427fc7 FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign 2023-10-27 15:42:24 +02:00
leonarski_f cf69aef472 FPGA: Add extra register slices for upside_down 2023-10-26 22:36:08 +02:00
leonarski_f 4e60bb2f9e FPGA: Add option to invert modules upside down 2023-10-25 22:20:45 +02:00
leonarski_f 6bcf54f603 FPGA: Add bitshuffle to the design (warning! no test for full integration!) 2023-10-25 11:07:21 +02:00
leonarski_f d408b3ed2a FPGA: Integrate add multipixel into the design 2023-10-24 18:58:59 +02:00
leonarski_f 3b65e6bf88 FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5) 2023-10-21 15:37:46 +02:00
leonarski_f 7008703af3 FPGA: Integration is not calculating sum2 2023-10-20 14:06:58 +02:00
leonarski_f f04f7a274b FPGA: Name spot finder signals in consistent manner 2023-10-19 20:52:09 +02:00
leonarski_f c7b7abb34d FPGA: Remove register slice for strong pixel result 2023-10-19 12:14:17 +02:00
leonarski_f 6f9f918ee6 HLS: Improve make scripts, so HLS test bench can be defined 2023-10-18 16:32:31 +02:00
leonarski_f 79df7cf7d5 FPGA: Add extra AXI-Stream register slices 2023-10-17 19:40:55 +02:00
leonarski_f c5ca10792e FPGA: Clean-up of spot_finder core + update README.MD 2023-10-16 15:13:47 +02:00
leonarski_f 7889f1666a FPGA: Spot finder 2nd version improved 2023-10-04 12:12:43 +02:00
leonarski_f c6afbebd13 FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result) 2023-10-02 22:34:49 +02:00
leonarski_f ca118f26d5 FPGA: integration results are reduced to cover two bins per 512-bit 2023-09-29 22:07:52 +02:00
leonarski_f 549cc6a887 FPGA: Add ADU histogram (work in progress; needs test) 2023-09-29 16:55:37 +02:00
leonarski_f 5bb92aed61 FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer 2023-09-29 14:44:08 +02:00
leonarski_f 79aef71ce3 FPGA: spot_finder added 2023-09-26 18:54:31 +02:00
leonarski_f 84bf69b8a6 FPGA: frame generator reads from HBM (work in progress) 2023-09-26 13:14:43 +02:00
leonarski_f 7e3b9cfeba Revert "FPGA: add spot finder to the design" 
This reverts commit df0b0d8b96.
 2023-09-25 21:52:55 +02:00
leonarski_f 027b3aa943 Revert "FPGA: add register slices" 
This reverts commit cf2163a402.
 2023-09-25 21:52:54 +02:00
leonarski_f cf2163a402 FPGA: add register slices 2023-09-24 20:28:35 +02:00
leonarski_f df0b0d8b96 FPGA: add spot finder to the design 2023-09-24 19:04:58 +02:00
leonarski_f ae6e036628 FPGA: increase frame_generator memory to 8 MiB 2023-09-24 14:39:46 +02:00
leonarski_f a70e3cf444 FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis 2023-09-22 21:49:41 +02:00
leonarski_f 2c9d623265 integration: use separate FIFO for integration results 2023-09-22 17:49:14 +02:00
leonarski_f 2eb85496f2 FPGA: add integration routine (work in progress) 2023-09-21 17:12:01 +02:00
leonarski_f 4d482e308a FPGA: Fix datamover script 2023-09-19 07:36:56 +02:00
leonarski_f 86123eb2fe FPGA: Use datamover for save_to_hbm and load_from_hbm 2023-09-19 07:36:56 +02:00
leonarski_f 98877e5bb3 FPGA: Monitor HBM completion and handle FIFOs 2023-09-19 07:36:56 +02:00
leonarski_f a80fd362a6 FPGA: Make sure all HBM handles are accessible - scale FIFOs properly 2023-09-19 07:36:56 +02:00