 leonarski_f
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ddf4c75645
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v1.0.0-rc.31
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2025-03-02 13:15:28 +01:00 |
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leonarski_f
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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leonarski_f
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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leonarski_f
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40c1e3d49f
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version 1.0.0-rc.20
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2024-10-21 13:30:56 +02:00 |
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leonarski_f
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3be959f272
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version 1.0.0-rc.14
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2024-10-07 11:56:40 +02:00 |
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leonarski_f
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e812918e2e
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version 1.0.0-rc.13
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2024-10-05 13:14:49 +02:00 |
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leonarski_f
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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leonarski_f
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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leonarski_f
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d66b6b949d
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Fix spot finding + fix FPGA network LEDs behavior
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2023-12-16 09:20:46 +01:00 |
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leonarski_f
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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leonarski_f
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39ca47aea9
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FPGA: Add processing stalls
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2023-11-21 15:42:26 +01:00 |
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leonarski_f
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e5397e68cf
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FPGA: Clean-up of HDL modules
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2023-11-18 19:18:26 +01:00 |
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leonarski_f
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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leonarski_f
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6bcf54f603
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FPGA: Add bitshuffle to the design (warning! no test for full integration!)
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2023-10-25 11:07:21 +02:00 |
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leonarski_f
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d408b3ed2a
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FPGA: Integrate add multipixel into the design
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2023-10-24 18:58:59 +02:00 |
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leonarski_f
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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leonarski_f
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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leonarski_f
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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leonarski_f
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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leonarski_f
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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leonarski_f
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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leonarski_f
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df0b0d8b96
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FPGA: add spot finder to the design
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2023-09-24 19:04:58 +02:00 |
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leonarski_f
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ae6e036628
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FPGA: increase frame_generator memory to 8 MiB
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2023-09-24 14:39:46 +02:00 |
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leonarski_f
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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leonarski_f
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86123eb2fe
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FPGA: Use datamover for save_to_hbm and load_from_hbm
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2023-09-19 07:36:56 +02:00 |
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leonarski_f
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36cd247377
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FPGA: Integrate HBM cache into the FPGA
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2023-09-19 07:36:56 +02:00 |
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leonarski_f
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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leonarski_f
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362eb62d4b
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FPGA: Use own function to merge streams instead of AXI-Switch + more FIFO status saved
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2023-09-14 23:58:17 +02:00 |
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leonarski_f
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496d016c31
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FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets)
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2023-09-13 20:06:09 +02:00 |
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leonarski_f
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9d01630cfc
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FPGA: load calibration works as dedicated function of the card
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2023-09-12 14:34:42 +02:00 |
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leonarski_f
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8c3a25a8ad
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FPGA: load calibration operates directly on HBM
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2023-09-11 21:47:29 +02:00 |
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leonarski_f
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05000bab1f
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FPGA: remove transfer to HBM for the time being
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2023-09-11 20:24:20 +02:00 |
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leonarski_f
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929f6c6544
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FPGA: Handle HBM offsets internally in Jungfraujoch logic
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2023-09-09 20:50:41 +02:00 |
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leonarski_f
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6251c58f32
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FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
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2023-09-08 19:08:37 +02:00 |
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leonarski_f
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e8c0500ea8
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FPGA: Use HBM switch to access full HBM
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2023-09-08 17:09:33 +02:00 |
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leonarski_f
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c2eaee6d8a
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FPGA: Save to HBM operates in parallel to host writer
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2023-09-08 13:07:49 +02:00 |
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leonarski_f
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38df621cf6
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FPGA: Add save to HBM (work in progress)
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2023-09-07 22:15:20 +02:00 |
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leonarski_f
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ae830009c4
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FPGA: Don't override default MAC location in bd_pcie.tcl
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2023-09-07 21:03:08 +02:00 |
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leonarski_f
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1d1894d7d6
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FPGA: Use only single HBM stack
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2023-09-07 21:03:08 +02:00 |
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leonarski_f
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dd002e3d6d
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FPGA: Build only 100G solution (no bifurcated design)
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2023-09-07 12:10:38 +02:00 |
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leonarski_f
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a6377239cf
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FPGA: fix script for 2x100G design
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2023-09-06 19:07:20 +02:00 |
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leonarski_f
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0434207882
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FPGA: use full AXI for internal packet generator
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2023-09-06 18:16:44 +02:00 |
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leonarski_f
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caf950f99f
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FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
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2023-09-06 08:19:03 +02:00 |
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leonarski_f
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3e406f0f46
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FPGA: URAM read latency reduced to 2
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2023-08-12 12:05:53 +02:00 |
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leonarski_f
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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