1786 Commits

Include renames

Author	SHA1	Message	Date
maliakal_d	7b44caab98	missed in previous commit	2026-04-30 08:52:20 +02:00
maliakal_d	d616549f87	tolerance process	2026-04-29 16:42:54 +02:00
maliakal_d	dc7ba60cc0	minor, default clk vals are 0 but set up at detector setup	2026-04-28 16:10:31 +02:00
maliakal_d	5360bf6d0f	minor, and binaries	2026-04-28 16:08:53 +02:00
maliakal_d	f6b67a8c0a	formatting	2026-04-27 17:00:02 +02:00
maliakal_d	b0f4aa1657	Merge branch 'developer' into dev/ctb_clocks	2026-04-27 16:58:44 +02:00
4 people	6bbbce5dc3	CTB: simplify power monitoring (#1428) ... * simplify power monitoring * removed register definitions not needed anymore, formatting * binaries updated --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>	2026-04-27 16:54:44 +02:00
muelle_m1	bd77ea231b	also added tolerance check for patwaittime	2026-04-24 15:07:49 +02:00
muelle_m1	795668be8a	insert tolerance check again	2026-04-24 13:42:13 +02:00
maliakal_dandGitHub	8ff128b062	Dev/ctb clocks fix (#1434) ... * introduced new type Hz, typetraits, String conversions, command generation (not yet generated) * incorrect unit typo * cmd generation and compiles * default to MHz, removed space between units for consistency with timers, min and max checks for clks * in python, but need to change the default to Hz again for clean code and intuition * allow ints, doubles, implicit conversions * dont allow raw ints, doubles and implicit conversions * fixed tests * added operators for Hz in python * fix test for min clk for xilinx ctb * fix test * fix python tests * fixed xilinx period and default clks * test fix * removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb * removing 3 clock cycle code from xilinx as well * formatting * loadpattern before 3 clk cycles code * actualtime and measurement time to be implemented in 100ns already in fw * fix tests * pyzmq dependency forthe tests * fixed pyctbgui for freq	2026-04-23 17:27:13 +02:00
maliakal_d	d1106fec41	Merge branch 'developer' into dev/ctb_clocks	2026-04-22 16:36:13 +02:00
3 people	c05d5a37cd	dev/ fix vchip and binaries (#1435) ... * updated binaries and fixed a warning by moving the usleep_bf to blackfin.c * suppressed warnings * cleaned up docs * renamed function --------- Co-authored-by: Alice <alice.mazzoleni@psi.ch>	2026-04-21 10:59:05 +02:00
3 people	78edfe3b55	Running Matterhorn on altera CTB (#1427) ... * testing matterhorn1 SPI on altera CTB, works for dummy-chip * added bf_usleep with proper timing for blackfin * simplified spi firmware interface, removed write and readstrobe * define constant for BFIN spi sleep --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch>	2026-04-15 16:23:04 +02:00
maliakal_dandGitHub	5ec5d46c48	Dev/ctb separate dac and power (#1420) ... * not allowing power names for dac names to prevent duplicate names * wip * v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power * binary in * dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands * wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested * wip. client and xilinx todo * wip: ctb power works, tests left * fixed some tests * added vchip check * python cmds still left. wip * fixed xilinx. python left * wip * wip. xilinx * fixed powerchip for ctb * power all returns all * configtransceiver is removed * wip python * wip * wip * wip * wip * wip * wip * wip xilinx * wip * wip * wip * pybindings * fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector * wip * fixed tests * fixes for python api * wip * python: moved powerlist to Ctb * fixed tests to work for powelist in Ctb * moved signallist, adclist, slowadc, slowadclist to Ctb * throw approperiate error when no modules added for powers * added dac test * fix dac default names and test for dacs * ctb dacs, yet to do othe rdacs * dacs should work now even in tests * run all tests * DetectorPowers->NamedPowers in ctb * comments * removed unnecessary test code * removed hard coded dac names in python NamedDacs and NamedPowers * minor * minor * fixed error messages * changed power to be able to set DAC directly, using enable and disable methods with enabled to get	2026-04-15 10:33:01 +02:00
muelle_m1	2372f93dd9	update help and comments	2026-03-19 15:23:50 +01:00
muelle_m1	614b5c56d9	change python and pyctbgui to accept and return floating point MHz	2026-03-19 15:10:03 +01:00
muelle_m1	6811bb1f33	added virtual check in Altera_PLL, update testcases	2026-03-19 11:49:47 +01:00
muelle_m1	0415911279	update default values in server defs	2026-03-19 11:30:40 +01:00
muelle_m1	27ea49c8e8	added tolerance to exptime, fixed test	2026-03-18 17:50:55 +01:00
muelle_m1	fc1f4b4a6a	change CTB and XCTB clock values to MHz, TODO: units and validation errors	2026-03-18 14:02:36 +01:00
muelle_m1	e2cb75c27d	Merge remote-tracking branch 'origin/developer' into dev/ctb_clocks	2026-03-18 10:05:51 +01:00
maliakal_dandGitHub	4ee61ae791	ctb and xilinx: setting all dacs (normal, not power dacs) to 0 (not power down) at startup. This is safer than power down for 4 normal dacs. xilinx ctb: remove disable fmc at power off chip so one can power on and off the chip on their own (#1424)	2026-03-17 16:53:33 +01:00
muelle_m1	6b13336c95	add check for backwards compatibility	2026-03-12 15:31:30 +01:00
muelle_m1	778b497eb1	added time for firmware to measrue actual value after frequency change	2026-03-12 15:13:52 +01:00
muelle_m1	f9b3c4f9ce	round CTB clocks to next closest possible value, added freq measurement	2026-03-11 17:57:20 +01:00
maliakal_dandGitHub	60f5db1224	xilinx: slow adcs (#1405) ... * xilinx: slow adcs * minor * xilinx: max reference voltage back to 2500mV for slow adcs ad7689	2026-02-27 17:17:11 +01:00
maliakal_dandGitHub	a3e6cc90ea	server versions werent getting updated (#1407)	2026-02-27 17:12:27 +01:00
maliakal_dandGitHub	a1c5bf971f	ctb: vchip doesnt validate with vlimit anymore (#1404)	2026-02-26 14:22:46 +01:00
maliakal_dandGitHub	8f07d2a464	Dev/xilinx set dac rewrite (#1389) ... * wip * wip * wip. xilinx left * wip. xilinx * wip * wip. compiles * fixed eiger test * more fixes * fixed virtual m3 * fix typos and bugs * setting power to 0 * set power fixed * updated server binaries * minor * refactoring * get vchip refactoring * eiger: unnecessary check for setsettings undefined * retval pointer for printout * eiger.wip, mV in boolean * wip. gotthard2 and m3 * wip. jungfrau * moench.wip * compiles.wip * fix eiger * m3 fix vthresh * fix ctband xilinx * default pwr index = pwr_io * minor:fn name and highvoltage to local var * refactor funcs * minor * minor * check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1 * minor * updated versioning * review changes: removing validateDACValue and other minor stuff * binaries in * wip * refactored m3 vth * minor review * minor review * m3 serverdac index fix * minor	2026-02-23 14:23:13 +01:00
maliakal_d	1c44a66964	formatted	2026-02-10 16:10:51 +01:00
Erik FröjdhandGitHub	3f4df445f1	send back the result of the SPI write (#1387)	2026-02-09 13:50:35 +01:00
Erik FröjdhandGitHub	0992c7ae4c	Read and write SPI for Xilinx CTB (#1381) ... -readSpi and writeSpi in C++ and Python API	2026-02-05 17:20:47 +01:00
muelle_m1	fb58fefe57	added RegDefs for 1G support on XCTB	2026-02-05 15:11:31 +01:00
maliakal_d	9e7952048a	calling setPower instead of setDac as the conversion should happen here	2026-01-28 15:20:34 +01:00
maliakal_d	9a876075ab	updated binary	2026-01-28 15:12:55 +01:00
maliakal_d	2c6ded89ad	xilinx server: not allowing power down as default dac values for the power regulators and not allowing to be set to these in the future either	2026-01-28 14:59:49 +01:00
maliakal_dandGitHub	55ff222437	Dev/server/separate list header (#1373) ... * xilinx, ctb and eiger server: detangled list.h to its own detector file * detangled list.h from all the detectors servers	2026-01-28 13:49:46 +01:00
maliakal_dandGitHub	b70d3c5ad3	xilinx: start state machine started with start_f bit in flow control and not anymore the start_p from matterhornspictrl reg (so now if the user messes up the pattern, it will be stuck forever) (#1366)	2026-01-22 10:00:25 +01:00
maliakal_dandGitHub	8769f1e70a	xilinx tsamples upper limit increased (#1365)	2026-01-21 16:13:22 +01:00
muelle_m1	0ba1139741	remove hardcoded MH02 startup	2026-01-13 11:05:37 +01:00
maliakal_dandGitHub	874ff353e5	virtual servers compile fix for xilinxfmc (#1352)	2026-01-06 14:38:11 +01:00
maliakal_d	66f9664bc4	fprintf should return 2 including terminating character as well. formatting.	2026-01-06 09:53:55 +01:00
maliakal_d	c154164eff	refactoring	2026-01-05 17:51:54 +01:00
muelle_m1	d95dff56e4	add back XCTB server binary	2026-01-05 17:03:50 +01:00
muelle_m1	bcd22af9ba	switch XCTB regDefs to cheby output	2026-01-05 13:53:30 +01:00
muelle_m1	dece2e16b4	update registerDefs.h	2026-01-05 09:31:32 +01:00
muelle_m1	8063560e3a	added FMC control	2025-11-26 12:16:30 +01:00
muelle_m1	af2c6eca0c	MH02 change clock switching method during periphery reset	2025-11-10 10:35:20 +01:00
Erik FröjdhandGitHub	d3dc92b18b	Using find_package(Threads REQUIRED) instead of linking pthread directly (#1324) ... * Linking to Threads::Threads instead of pthread directly * moved rt linking to slsSupportObject and only enable for linux	2025-10-27 16:30:40 +01:00
maliakal_dandGitHub	5041fd7fef	Dev/xilinx set power (#1316) ... * ctb updates not in release notes * xilinx power similar to ctb,except no vchip	2025-10-16 13:57:11 +02:00