mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-05-07 05:24:13 +02:00
Merge branch 'developer' into dev/ctb_clocks
This commit is contained in:
@@ -12,8 +12,6 @@ add_executable(ctbDetectorServer_virtual
|
||||
../slsDetectorServer/src/UDPPacketHeaderGenerator.c
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||||
../slsDetectorServer/src/AD9257.c
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||||
../slsDetectorServer/src/ALTERA_PLL.c
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||||
../slsDetectorServer/src/I2C.c
|
||||
../slsDetectorServer/src/INA226.c
|
||||
../slsDetectorServer/src/LTC2620.c
|
||||
../slsDetectorServer/src/MAX1932.c
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||||
../slsDetectorServer/src/programViaBlackfin.c
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||||
@@ -16,7 +16,7 @@ DESTDIR ?= bin
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INSTMODE = 0777
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||||
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SRCS = slsDetectorFunctionList.c
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SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)blackfin.c $(main_src)common.c $(main_src)commonServerFunctions.c $(main_src)communication_funcs_UDP.c $(main_src)UDPPacketHeaderGenerator.c $(main_src)AD9257.c $(main_src)ALTERA_PLL.c $(main_src)I2C.c $(main_src)INA226.c $(main_src)LTC2620.c $(main_src)MAX1932.c $(main_src)programViaBlackfin.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c
|
||||
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)blackfin.c $(main_src)common.c $(main_src)commonServerFunctions.c $(main_src)communication_funcs_UDP.c $(main_src)UDPPacketHeaderGenerator.c $(main_src)AD9257.c $(main_src)ALTERA_PLL.c $(main_src)LTC2620.c $(main_src)MAX1932.c $(main_src)programViaBlackfin.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c
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||||
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OBJS = $(SRCS:.c=.o)
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@@ -639,16 +639,8 @@
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#define SPI_WRITEDATA_REG (0x49 << MEM_MAP_SHIFT)
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#define SPI_READDATA_REG (0x4A << MEM_MAP_SHIFT)
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/** I2C Control register */
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#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
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#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
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#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
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#define I2C_STATUS_REG (0x105 << MEM_MAP_SHIFT)
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#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
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#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
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#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
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#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
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// fixme: upto 0x10f
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/* Power monitor base register */
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#define POWER_MONITOR_BASE_REG (0x50 << MEM_MAP_SHIFT)
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/* Round Robin */
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#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
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Binary file not shown.
@@ -6,7 +6,6 @@
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#include "sls/versionAPI.h"
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#include "ALTERA_PLL.h" // pll
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#include "INA226.h" // i2c
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#include "LTC2620.h" // dacs
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#include "MAX1932.h" // hv
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#include "UDPPacketHeaderGenerator.h"
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@@ -616,17 +615,6 @@ void setupDetector() {
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return;
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}
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// I2C
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INA226_ConfigureI2CCore(I2C_SHUNT_RESISTER_OHMS, I2C_CONTROL_REG,
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I2C_STATUS_REG, I2C_RX_DATA_FIFO_REG,
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I2C_RX_DATA_FIFO_LEVEL_REG, I2C_SCL_LOW_COUNT_REG,
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I2C_SCL_HIGH_COUNT_REG, I2C_SDA_HOLD_REG,
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I2C_TRANSFER_COMMAND_FIFO_REG);
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INA226_CalibrateCurrentRegister(I2C_POWER_VIO_DEVICE_ID);
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INA226_CalibrateCurrentRegister(I2C_POWER_VA_DEVICE_ID);
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INA226_CalibrateCurrentRegister(I2C_POWER_VB_DEVICE_ID);
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INA226_CalibrateCurrentRegister(I2C_POWER_VC_DEVICE_ID);
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INA226_CalibrateCurrentRegister(I2C_POWER_VD_DEVICE_ID);
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initError = setVchip(VCHIP_MIN_MV, initErrorMessage);
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if (initError == FAIL)
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return;
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@@ -1777,26 +1765,35 @@ int getPowerADC(enum powerIndex index, int *retval, char *mess) {
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enum ADCINDEX adcIndex = V_PWR_IO;
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switch (index) {
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case V_POWER_A:
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case I_POWER_A:
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adcIndex = V_PWR_A;
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break;
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case V_POWER_B:
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case I_POWER_B:
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adcIndex = V_PWR_B;
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break;
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case V_POWER_C:
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case I_POWER_C:
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adcIndex = V_PWR_C;
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break;
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case V_POWER_D:
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case I_POWER_D:
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adcIndex = V_PWR_D;
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break;
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case V_POWER_IO:
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case I_POWER_IO:
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adcIndex = V_PWR_IO;
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break;
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case I_POWER_A:
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adcIndex = I_PWR_A;
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break;
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case I_POWER_B:
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adcIndex = I_PWR_B;
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break;
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case I_POWER_C:
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adcIndex = I_PWR_C;
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break;
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case I_POWER_D:
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adcIndex = I_PWR_D;
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break;
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case I_POWER_IO:
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adcIndex = I_PWR_IO;
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break;
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default:
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sprintf(mess, "Could not get Power ADC. Invalid index %d\n", index);
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LOG(logERROR, (mess));
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@@ -1806,17 +1803,7 @@ int getPowerADC(enum powerIndex index, int *retval, char *mess) {
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#ifdef VIRTUAL
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return 0;
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#endif
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int deviceId = I2C_POWER_VIO_DEVICE_ID + (int)adcIndex;
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// adc voltage
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if (index < I_POWER_A) {
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LOG(logDEBUG1, ("Reading I2C Voltage for device Id: %d\n", deviceId));
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*retval = INA226_ReadVoltage(deviceId);
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return OK;
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}
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// adc current
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LOG(logDEBUG1, ("Reading I2C Current for device Id: %d\n", deviceId));
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||||
*retval = INA226_ReadCurrent(deviceId);
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*retval = bus_r(POWER_MONITOR_BASE_REG + ((int)adcIndex << MEM_MAP_SHIFT));
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||||
return OK;
|
||||
}
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||||
|
||||
|
||||
@@ -18,24 +18,18 @@
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||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
|
||||
/* Hardware Definitions */
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||||
#define NCHAN (40)
|
||||
#define NCHAN_ANALOG (32)
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||||
#define NCHAN_DIGITAL (64)
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||||
#define NCHAN_TRANSCEIVER (4)
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||||
#define NBITS_PER_TRANSCEIVER (64)
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#define NCHIP (1)
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#define NDAC (24)
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#define NPWR (6)
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#define NDAC_ONLY (NDAC - NPWR)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) // MHz
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#define I2C_POWER_VIO_DEVICE_ID (0x40)
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#define I2C_POWER_VA_DEVICE_ID (0x41)
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#define I2C_POWER_VB_DEVICE_ID (0x42)
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||||
#define I2C_POWER_VC_DEVICE_ID (0x43)
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||||
#define I2C_POWER_VD_DEVICE_ID (0x44)
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#define I2C_SHUNT_RESISTER_OHMS (0.005)
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#define NCHAN (40)
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#define NCHAN_ANALOG (32)
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#define NCHAN_DIGITAL (64)
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#define NCHAN_TRANSCEIVER (4)
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#define NBITS_PER_TRANSCEIVER (64)
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#define NCHIP (1)
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#define NDAC (24)
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#define NPWR (6)
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#define NDAC_ONLY (NDAC - NPWR)
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||||
#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) // MHz
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||||
|
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/** Default Parameters */
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||||
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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@@ -1,38 +0,0 @@
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// SPDX-License-Identifier: LGPL-3.0-or-other
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
||||
#pragma once
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|
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#include <inttypes.h>
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|
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/**
|
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* Configure the I2C core,
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* Enable core and
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* Calibrate the calibration register for current readout
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||||
* @param creg control register (defined in RegisterDefs.h)
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||||
* @param sreg status register (defined in RegisterDefs.h)
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||||
* @param rreg rx data fifo register (defined in RegisterDefs.h)
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* @param rlvlreg rx data fifo level register (defined in RegisterDefs.h)
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||||
* @param slreg scl low count register (defined in RegisterDefs.h)
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||||
* @param shreg scl high count register (defined in RegisterDefs.h)
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* @param sdreg sda hold register (defined in RegisterDefs.h)
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* @param treg transfer command fifo register (defined in RegisterDefs.h)
|
||||
*/
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void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
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uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
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uint32_t sdreg, uint32_t treg);
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|
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/**
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* Read register
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* @param deviceId device Id
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||||
* @param addr register address
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* @returns value read from register
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*/
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uint32_t I2C_Read(uint32_t devId, uint32_t addr);
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/**
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* Write register (16 bit value)
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* @param deviceId device Id
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* @param addr register address
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* @param data data to be written (16 bit)
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*/
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void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data);
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@@ -1,42 +0,0 @@
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// SPDX-License-Identifier: LGPL-3.0-or-other
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
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#pragma once
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#include <inttypes.h>
|
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|
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/**
|
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* Configure the I2C core and Enable core
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* @param rOhm shunt resister value in Ohms (defined in
|
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* slsDetectorServer_defs.h)
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* @param creg control register (defined in RegisterDefs.h)
|
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* @param sreg status register (defined in RegisterDefs.h)
|
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* @param rreg rx data fifo register (defined in RegisterDefs.h)
|
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* @param rlvlreg rx data fifo level register (defined in RegisterDefs.h)
|
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* @param slreg scl low count register (defined in RegisterDefs.h)
|
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* @param shreg scl high count register (defined in RegisterDefs.h)
|
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* @param sdreg sda hold register (defined in RegisterDefs.h)
|
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* @param treg transfer command fifo register (defined in RegisterDefs.h)
|
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*/
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void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
|
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uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
|
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uint32_t shreg, uint32_t sdreg, uint32_t treg);
|
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|
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/**
|
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* Calibrate resolution of current register
|
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* @param deviceId device Id (defined in slsDetectorServer_defs.h)
|
||||
*/
|
||||
void INA226_CalibrateCurrentRegister(uint32_t deviceId);
|
||||
|
||||
/**
|
||||
* Read voltage of device
|
||||
* @param deviceId device Id
|
||||
* @returns voltage in mV
|
||||
*/
|
||||
int INA226_ReadVoltage(uint32_t deviceId);
|
||||
|
||||
/**
|
||||
* Read current
|
||||
* @param deviceId device Id
|
||||
* @returns current in mA
|
||||
*/
|
||||
int INA226_ReadCurrent(uint32_t deviceId);
|
||||
@@ -22,9 +22,6 @@
|
||||
#define BFIN_AMC_ACCESS_EXTENSION_FNAME \
|
||||
"/sys/kernel/debug/blackfin/ebiu_amc/EBIU_AMBCTL1"
|
||||
|
||||
/** I2C defines */
|
||||
#define I2C_CLOCK_MHZ (131.25)
|
||||
|
||||
/**
|
||||
* Write into a 16 bit register
|
||||
* @param offset address offset
|
||||
|
||||
@@ -1,293 +0,0 @@
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-other
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
||||
#include "I2C.h"
|
||||
#include "blackfin.h"
|
||||
#include "clogger.h"
|
||||
|
||||
#include <unistd.h> // usleep
|
||||
|
||||
/**
|
||||
* Intel: Embedded Peripherals IP User Guide
|
||||
* https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf
|
||||
* To be defined
|
||||
*
|
||||
* (in blackfin.h)
|
||||
* I2C_CLOCK_MHZ
|
||||
*
|
||||
* (RegisterDefs.h)
|
||||
* I2C_SCL_LOW_COUNT_REG
|
||||
* I2C_SCL_HIGH_COUNT_REG
|
||||
* I2C_SDA_HOLD_REG
|
||||
* I2C_CONTROL_REG
|
||||
* I2C_STATUS_REG
|
||||
* I2C_TRANSFER_COMMAND_FIFO_REG
|
||||
* I2C_RX_DATA_FIFO_LEVEL_REG
|
||||
* I2C_RX_DATA_FIFO_REG
|
||||
*/
|
||||
|
||||
#define I2C_DATA_RATE_KBPS (200)
|
||||
|
||||
/** Control Register */
|
||||
#define I2C_CTRL_ENBLE_CORE_OFST (0)
|
||||
#define I2C_CTRL_ENBLE_CORE_MSK (0x00000001 << I2C_CTRL_ENBLE_CORE_OFST)
|
||||
#define I2C_CTRL_BUS_SPEED_OFST (1)
|
||||
#define I2C_CTRL_BUS_SPEED_MSK (0x00000001 << I2C_CTRL_BUS_SPEED_OFST)
|
||||
#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL \
|
||||
((0x0 << I2C_CTRL_BUS_SPEED_OFST) & \
|
||||
I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
|
||||
#define I2C_CTRL_BUS_SPEED_FAST_400_VAL \
|
||||
((0x1 << I2C_CTRL_BUS_SPEED_OFST) & \
|
||||
I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
|
||||
/** if actual level of transfer command fifo <= thd level, TX_READY interrupt
|
||||
* asserted */
|
||||
#define I2C_CTRL_TFR_CMD_FIFO_THD_OFST (2)
|
||||
#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK \
|
||||
(0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
|
||||
#define I2C_CTRL_TFR_CMD_EMPTY_VAL \
|
||||
((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
|
||||
#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL \
|
||||
((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
|
||||
#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL \
|
||||
((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
|
||||
#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL \
|
||||
((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
|
||||
/** if actual level of receive data fifo <= thd level, RX_READY interrupt
|
||||
* asserted */
|
||||
#define I2C_CTRL_RX_DATA_FIFO_THD_OFST (4)
|
||||
#define I2C_CTRL_RX_DATA_FIFO_THD_MSK \
|
||||
(0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
|
||||
#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL \
|
||||
((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
|
||||
#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL \
|
||||
((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
|
||||
#define I2C_CTRL_RX_DATA_ONE_HALF_VAL \
|
||||
((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
|
||||
#define I2C_CTRL_RX_DATA_FULL_VAL \
|
||||
((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
|
||||
|
||||
/** Transfer Command Fifo register */
|
||||
#define I2C_TFR_CMD_RW_OFST (0)
|
||||
#define I2C_TFR_CMD_RW_MSK (0x00000001 << I2C_TFR_CMD_RW_OFST)
|
||||
#define I2C_TFR_CMD_RW_WRITE_VAL \
|
||||
((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
|
||||
#define I2C_TFR_CMD_RW_READ_VAL \
|
||||
((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
|
||||
#define I2C_TFR_CMD_ADDR_OFST (1)
|
||||
#define I2C_TFR_CMD_ADDR_MSK (0x0000007F << I2C_TFR_CMD_ADDR_OFST)
|
||||
/** when writing, rw and addr converts to data to be written mask */
|
||||
#define I2C_TFR_CMD_DATA_FR_WR_OFST (0)
|
||||
#define I2C_TFR_CMD_DATA_FR_WR_MSK (0x000000FF << I2C_TFR_CMD_DATA_FR_WR_OFST)
|
||||
#define I2C_TFR_CMD_STOP_OFST (8)
|
||||
#define I2C_TFR_CMD_STOP_MSK (0x00000001 << I2C_TFR_CMD_STOP_OFST)
|
||||
#define I2C_TFR_CMD_RPTD_STRT_OFST (9)
|
||||
#define I2C_TFR_CMD_RPTD_STRT_MSK (0x00000001 << I2C_TFR_CMD_RPTD_STRT_OFST)
|
||||
|
||||
/** Receive DataFifo register */
|
||||
#define I2C_RX_DATA_FIFO_RXDATA_OFST (0)
|
||||
#define I2C_RX_DATA_FIFO_RXDATA_MSK (0x000000FF << I2C_RX_DATA_FIFO_RXDATA_OFST)
|
||||
|
||||
/** Status register */
|
||||
#define I2C_STATUS_BUSY_OFST (0)
|
||||
#define I2C_STATUS_BUSY_MSK (0x00000001 << I2C_STATUS_BUSY_OFST)
|
||||
|
||||
/** SCL Low Count register */
|
||||
#define I2C_SCL_LOW_COUNT_PERIOD_OFST (0)
|
||||
#define I2C_SCL_LOW_COUNT_PERIOD_MSK \
|
||||
(0x0000FFFF << I2C_SCL_LOW_COUNT_PERIOD_OFST)
|
||||
|
||||
/** SCL High Count register */
|
||||
#define I2C_SCL_HIGH_COUNT_PERIOD_OFST (0)
|
||||
#define I2C_SCL_HIGH_COUNT_PERIOD_MSK \
|
||||
(0x0000FFFF << I2C_SCL_HIGH_COUNT_PERIOD_OFST)
|
||||
|
||||
/** SDA Hold Count register */
|
||||
#define I2C_SDA_HOLD_COUNT_PERIOD_OFST (0)
|
||||
#define I2C_SDA_HOLD_COUNT_PERIOD_MSK \
|
||||
(0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST)
|
||||
|
||||
/** Receive Data Fifo Level register */
|
||||
// #define I2C_RX_DATA_FIFO_LVL_OFST (0)
|
||||
// #define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF <<
|
||||
// I2C_RX_DATA_FIFO_LVL_OFST)
|
||||
|
||||
// defines in the fpga
|
||||
uint32_t I2C_Control_Reg = 0x0;
|
||||
uint32_t I2C_Status_Reg = 0x0;
|
||||
uint32_t I2C_Rx_Data_Fifo_Reg = 0x0;
|
||||
uint32_t I2C_Rx_Data_Fifo_Level_Reg = 0x0;
|
||||
uint32_t I2C_Scl_Low_Count_Reg = 0x0;
|
||||
uint32_t I2C_Scl_High_Count_Reg = 0x0;
|
||||
uint32_t I2C_Sda_Hold_Reg = 0x0;
|
||||
uint32_t I2C_Transfer_Command_Fifo_Reg = 0x0;
|
||||
|
||||
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
|
||||
uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
|
||||
uint32_t sdreg, uint32_t treg) {
|
||||
LOG(logINFO, ("\tConfiguring I2C Core for %d kbps:\n", I2C_DATA_RATE_KBPS));
|
||||
LOG(logDEBUG1, ("controlreg,:0x%x, statusreg,:0x%x, "
|
||||
"rxrdatafiforeg: 0x%x, rxdatafifocountreg,:0x%x, "
|
||||
"scllow,:0x%x, sclhighreg,:0x%x, sdaholdreg,:0x%x, "
|
||||
"transfercmdreg,:0x%x\n",
|
||||
creg, sreg, rreg, rlvlreg, slreg, shreg, sdreg, treg));
|
||||
|
||||
I2C_Control_Reg = creg;
|
||||
I2C_Status_Reg = sreg;
|
||||
I2C_Rx_Data_Fifo_Reg = rreg;
|
||||
I2C_Rx_Data_Fifo_Level_Reg = rlvlreg;
|
||||
I2C_Scl_Low_Count_Reg = slreg;
|
||||
I2C_Scl_High_Count_Reg = shreg;
|
||||
I2C_Sda_Hold_Reg = sdreg;
|
||||
I2C_Transfer_Command_Fifo_Reg = treg;
|
||||
|
||||
// calculate scl low and high period count
|
||||
uint32_t sclPeriodNs = ((1000.00 * 1000.00 * 1000.00) /
|
||||
((double)I2C_DATA_RATE_KBPS * 1000.00));
|
||||
// scl low period same as high period
|
||||
uint32_t sclLowPeriodNs = sclPeriodNs / 2;
|
||||
// convert to us, then to clock (defined in blackfin.h)
|
||||
uint32_t sclLowPeriodCount = (sclLowPeriodNs / 1000.00) * I2C_CLOCK_MHZ;
|
||||
|
||||
// calculate sda hold data count
|
||||
uint32_t sdaDataHoldTimeNs =
|
||||
(sclLowPeriodNs / 2); // scl low period same as high period
|
||||
// convert to us, then to clock (defined in blackfin.h)
|
||||
uint32_t sdaDataHoldCount = ((sdaDataHoldTimeNs / 1000.00) * I2C_CLOCK_MHZ);
|
||||
|
||||
LOG(logINFO, ("\tSetting SCL Low Period: %d ns (%d clocks)\n",
|
||||
sclLowPeriodNs, sclLowPeriodCount));
|
||||
bus_w(I2C_Scl_Low_Count_Reg,
|
||||
bus_r(I2C_Scl_Low_Count_Reg) |
|
||||
((sclLowPeriodCount << I2C_SCL_LOW_COUNT_PERIOD_OFST) &
|
||||
I2C_SCL_LOW_COUNT_PERIOD_MSK));
|
||||
LOG(logDEBUG1, ("SCL Low reg:0x%x\n", bus_r(I2C_Scl_Low_Count_Reg)));
|
||||
|
||||
LOG(logINFO, ("\tSetting SCL High Period: %d ns (%d clocks)\n",
|
||||
sclLowPeriodNs, sclLowPeriodCount));
|
||||
bus_w(I2C_Scl_High_Count_Reg,
|
||||
bus_r(I2C_Scl_High_Count_Reg) |
|
||||
((sclLowPeriodCount << I2C_SCL_HIGH_COUNT_PERIOD_OFST) &
|
||||
I2C_SCL_HIGH_COUNT_PERIOD_MSK));
|
||||
LOG(logDEBUG1, ("SCL High reg:0x%x\n", bus_r(I2C_Scl_High_Count_Reg)));
|
||||
|
||||
LOG(logINFO, ("\tSetting SDA Hold Time: %d ns (%d clocks)\n",
|
||||
sdaDataHoldTimeNs, sdaDataHoldCount));
|
||||
bus_w(I2C_Sda_Hold_Reg,
|
||||
bus_r(I2C_Sda_Hold_Reg) |
|
||||
((sdaDataHoldCount << I2C_SDA_HOLD_COUNT_PERIOD_OFST) &
|
||||
I2C_SDA_HOLD_COUNT_PERIOD_MSK));
|
||||
LOG(logDEBUG1, ("SDA Hold reg:0x%x\n", bus_r(I2C_Sda_Hold_Reg)));
|
||||
|
||||
LOG(logINFO, ("\tEnabling core and bus speed to fast (up to 400 kbps)\n"));
|
||||
bus_w(I2C_Control_Reg,
|
||||
bus_r(I2C_Control_Reg) | I2C_CTRL_ENBLE_CORE_MSK |
|
||||
I2C_CTRL_BUS_SPEED_FAST_400_VAL); // fixme: (works?)
|
||||
LOG(logDEBUG1, ("Control reg:0x%x\n", bus_r(I2C_Control_Reg)));
|
||||
// The INA226 supports the transmission protocol for fast mode (1 kHz to 400
|
||||
// kHz) and high-speed mode (1 kHz to 2.94 MHz).
|
||||
}
|
||||
|
||||
uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
|
||||
LOG(logDEBUG2, (" ================================================\n"));
|
||||
LOG(logDEBUG2,
|
||||
(" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
|
||||
// device Id mask
|
||||
uint32_t devIdMask =
|
||||
((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
|
||||
LOG(logDEBUG2, (" devId:0x%x\n", devIdMask));
|
||||
|
||||
// write I2C ID
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
|
||||
LOG(logDEBUG2,
|
||||
(" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
|
||||
|
||||
// write register addr
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
|
||||
LOG(logDEBUG2, (" write addr:0x%x\n", addr));
|
||||
|
||||
// repeated start with read (repeated start needed here because it was in
|
||||
// write operation mode earlier, for the device ID)
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg,
|
||||
(devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
|
||||
LOG(logDEBUG2,
|
||||
(" repeated start:0x%x\n",
|
||||
(devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
|
||||
|
||||
// continue reading
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg, 0x0);
|
||||
LOG(logDEBUG2, (" continue reading:0x%x\n", 0x0));
|
||||
|
||||
// stop reading
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg, I2C_TFR_CMD_STOP_MSK);
|
||||
LOG(logDEBUG2, (" stop reading:0x%x\n", I2C_TFR_CMD_STOP_MSK));
|
||||
|
||||
// read value
|
||||
uint32_t retval = 0;
|
||||
|
||||
// In case one wants to do something more general (INA226 receives only 2
|
||||
// bytes)
|
||||
// wait till status is idle
|
||||
int status = 1;
|
||||
while (status) {
|
||||
status = bus_r(I2C_Status_Reg) & I2C_STATUS_BUSY_MSK;
|
||||
LOG(logDEBUG2, (" status:%d\n", status));
|
||||
usleep(0);
|
||||
}
|
||||
// get rx fifo level (get number of bytes to be received)
|
||||
int level = bus_r(I2C_Rx_Data_Fifo_Level_Reg);
|
||||
LOG(logDEBUG2, (" level:%d\n", level));
|
||||
|
||||
// level bytes to read, read 1 byte at a time
|
||||
for (int iloop = level - 1; iloop >= 0; --iloop) {
|
||||
u_int16_t byte =
|
||||
bus_r(I2C_Rx_Data_Fifo_Reg) & I2C_RX_DATA_FIFO_RXDATA_MSK;
|
||||
LOG(logDEBUG2, (" byte nr %d:0x%x\n", iloop, byte));
|
||||
// push by 1 byte at a time
|
||||
retval |= (byte << (8 * iloop));
|
||||
}
|
||||
LOG(logDEBUG2, (" retval:0x%x\n", retval));
|
||||
LOG(logDEBUG2, (" ================================================\n"));
|
||||
return retval;
|
||||
}
|
||||
|
||||
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data) {
|
||||
LOG(logDEBUG2, (" ================================================\n"));
|
||||
LOG(logDEBUG2, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId,
|
||||
addr, data));
|
||||
// device Id mask
|
||||
uint32_t devIdMask =
|
||||
((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
|
||||
LOG(logDEBUG2, (" devId:0x%x\n", devId));
|
||||
|
||||
// write I2C ID
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
|
||||
LOG(logDEBUG2,
|
||||
(" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
|
||||
|
||||
// write register addr
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
|
||||
LOG(logDEBUG2, (" write addr:0x%x\n", addr));
|
||||
|
||||
// do not do the repeated start as it is already in write operation mode
|
||||
// (else it wont work)
|
||||
|
||||
uint8_t msb = (uint8_t)((data & 0xFF00) >> 8);
|
||||
uint8_t lsb = (uint8_t)(data & 0x00FF);
|
||||
LOG(logDEBUG2, (" msb:0x%02x, lsb:0x%02x\n", msb, lsb));
|
||||
|
||||
// writing data MSB
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg,
|
||||
((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
|
||||
LOG(logDEBUG2,
|
||||
(" write msb:0x%02x\n",
|
||||
((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
|
||||
|
||||
// writing data LSB and stop writing bit
|
||||
bus_w(I2C_Transfer_Command_Fifo_Reg,
|
||||
((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) |
|
||||
I2C_TFR_CMD_STOP_MSK);
|
||||
LOG(logDEBUG2,
|
||||
(" write lsb and stop writing:0x%x\n",
|
||||
((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) |
|
||||
I2C_TFR_CMD_STOP_MSK));
|
||||
LOG(logDEBUG2, (" ================================================\n"));
|
||||
}
|
||||
@@ -1,173 +0,0 @@
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-other
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
||||
#include "INA226.h"
|
||||
#include "I2C.h"
|
||||
#include "clogger.h"
|
||||
#include "common.h"
|
||||
|
||||
#include "math.h"
|
||||
|
||||
/**
|
||||
* To be defined in
|
||||
*
|
||||
* (slsDetectorServer_defs.h)
|
||||
* I2C_SHUNT_RESISTER_OHMS
|
||||
* device ids that are passed as arguments
|
||||
*/
|
||||
|
||||
/** INA226 defines */
|
||||
|
||||
/** Register set */
|
||||
#define INA226_CONFIGURATION_REG (0x00) // R/W
|
||||
#define INA226_SHUNT_VOLTAGE_REG (0x01) // R
|
||||
#define INA226_BUS_VOLTAGE_REG (0x02) // R
|
||||
#define INA226_POWER_REG (0x03) // R
|
||||
#define INA226_CURRENT_REG (0x04) // R
|
||||
#define INA226_CALIBRATION_REG (0x05) // R/W
|
||||
#define INA226_MASK_ENABLE_REG (0x06) // R/W
|
||||
#define INA226_ALERT_LIMIT_REG (0x07) // R/W
|
||||
#define INA226_MANUFACTURER_ID_REG (0xFE) // R
|
||||
#define INA226_DIE_ID_REG (0xFF) // R
|
||||
|
||||
/** bus voltage register */
|
||||
#define INA226_BUS_VOLTAGE_VMIN_UV (1250) // 1.25mV
|
||||
#define INA226_BUS_VOLTAGE_MX_STPS (0x7FFF + 1)
|
||||
#define INA226_BUS_VOLTAGE_VMAX_UV \
|
||||
(INA226_BUS_VOLTAGE_VMIN_UV * \
|
||||
INA226_BUS_VOLTAGE_MX_STPS) // 40960000uV, 40.96V
|
||||
|
||||
/** shunt voltage register */
|
||||
#define INA226_SHUNT_VOLTAGE_VMIN_NV (2500) // 2.5uV
|
||||
#define INA226_SHUNT_VOLTAGE_MX_STPS (0x7FFF + 1)
|
||||
#define INA226_SHUNT_VOLTAGE_VMAX_NV \
|
||||
(INA226_SHUNT_VOLTAGE_VMIN_NV * \
|
||||
INA226_SHUNT_VOLTAGE_MX_STPS) // 81920000nV, 81.92mV
|
||||
#define INA226_SHUNT_NEGATIVE_MSK (1 << 15)
|
||||
#define INA226_SHUNT_ABS_VALUE_MSK (0x7FFF)
|
||||
|
||||
/** current precision for calibration register */
|
||||
#define INA226_CURRENT_IMIN_UA (100) // 100uA can be changed
|
||||
|
||||
/** calibration register */
|
||||
#define INA226_CALIBRATION_MSK (0x7FFF)
|
||||
|
||||
/** get calibration register value to be set */
|
||||
#define INA226_getCalibrationValue(rOhm) \
|
||||
(0.00512 / (INA226_CURRENT_IMIN_UA * 1e-6 * rOhm))
|
||||
|
||||
/** get current unit */
|
||||
#define INA226_getConvertedCurrentUnits(shuntV, calibReg) \
|
||||
((double)shuntV * (double)calibReg / (double)2048)
|
||||
|
||||
// defines from the fpga
|
||||
double INA226_Shunt_Resistor_Ohm = 0.0;
|
||||
int INA226_Calibration_Register_Value = 0;
|
||||
|
||||
#define INA226_CALIBRATION_CURRENT_TOLERANCE (1.2268)
|
||||
|
||||
void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
|
||||
uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
|
||||
uint32_t shreg, uint32_t sdreg, uint32_t treg) {
|
||||
LOG(logINFOBLUE, ("Configuring INA226\n"));
|
||||
LOG(logDEBUG1, ("Shunt ohm resistor: %f\n", rOhm));
|
||||
INA226_Shunt_Resistor_Ohm = rOhm;
|
||||
|
||||
I2C_ConfigureI2CCore(creg, sreg, rreg, rlvlreg, slreg, shreg, sdreg, treg);
|
||||
}
|
||||
|
||||
void INA226_CalibrateCurrentRegister(uint32_t deviceId) {
|
||||
LOG(logINFO,
|
||||
("Calibrating Current Register for Device ID: 0x%x\n", deviceId));
|
||||
// get calibration value based on shunt resistor
|
||||
uint16_t calVal =
|
||||
((uint16_t)INA226_getCalibrationValue(INA226_Shunt_Resistor_Ohm)) &
|
||||
INA226_CALIBRATION_MSK;
|
||||
LOG(logINFO,
|
||||
("\tCalculated calibration reg value: 0x%0x (%d)\n", calVal, calVal));
|
||||
|
||||
calVal = ((double)calVal / INA226_CALIBRATION_CURRENT_TOLERANCE) + 0.5;
|
||||
LOG(logINFO,
|
||||
("\tRealculated (for tolerance) calibration reg value: 0x%0x (%d)\n",
|
||||
calVal, calVal));
|
||||
INA226_Calibration_Register_Value = calVal;
|
||||
|
||||
// calibrate current register
|
||||
I2C_Write(deviceId, INA226_CALIBRATION_REG, calVal);
|
||||
|
||||
// read back calibration register
|
||||
int retval = I2C_Read(deviceId, INA226_CALIBRATION_REG);
|
||||
if (retval != calVal) {
|
||||
LOG(logERROR,
|
||||
("Cannot set calibration register for I2C. Set 0x%x, read 0x%x\n",
|
||||
calVal, retval));
|
||||
}
|
||||
}
|
||||
|
||||
int INA226_ReadVoltage(uint32_t deviceId) {
|
||||
LOG(logDEBUG1, (" Reading voltage\n"));
|
||||
uint32_t regval = I2C_Read(deviceId, INA226_BUS_VOLTAGE_REG);
|
||||
LOG(logDEBUG1, (" bus voltage reg: 0x%08x\n", regval));
|
||||
|
||||
// value in uV
|
||||
int voltageuV = 0;
|
||||
ConvertToDifferentRange(0, INA226_BUS_VOLTAGE_MX_STPS,
|
||||
INA226_BUS_VOLTAGE_VMIN_UV,
|
||||
INA226_BUS_VOLTAGE_VMAX_UV, regval, &voltageuV);
|
||||
LOG(logDEBUG1, (" voltage: 0x%d uV\n", voltageuV));
|
||||
|
||||
// value in mV
|
||||
int voltagemV = voltageuV / 1000;
|
||||
LOG(logDEBUG1, (" voltage: %d mV\n", voltagemV));
|
||||
LOG(logINFO,
|
||||
("Voltage via I2C (Device: 0x%x): %d mV\n", deviceId, voltagemV));
|
||||
|
||||
return voltagemV;
|
||||
}
|
||||
|
||||
int INA226_ReadCurrent(uint32_t deviceId) {
|
||||
LOG(logDEBUG1, (" Reading current\n"));
|
||||
|
||||
// read shunt voltage register
|
||||
LOG(logDEBUG1, (" Reading shunt voltage reg\n"));
|
||||
uint32_t shuntVoltageRegVal = I2C_Read(deviceId, INA226_SHUNT_VOLTAGE_REG);
|
||||
LOG(logDEBUG1, (" shunt voltage reg: %d\n", shuntVoltageRegVal));
|
||||
|
||||
// read it once more as this error has occured once
|
||||
if (shuntVoltageRegVal == 0xFFFF) {
|
||||
LOG(logDEBUG1, (" Reading shunt voltage reg again\n"));
|
||||
shuntVoltageRegVal = I2C_Read(deviceId, INA226_SHUNT_VOLTAGE_REG);
|
||||
LOG(logDEBUG1, (" shunt voltage reg: %d\n", shuntVoltageRegVal));
|
||||
}
|
||||
// value for current
|
||||
int retval = INA226_getConvertedCurrentUnits(
|
||||
shuntVoltageRegVal, INA226_Calibration_Register_Value);
|
||||
LOG(logDEBUG1, (" current unit value: %d\n", retval));
|
||||
|
||||
// reading directly the current reg
|
||||
LOG(logDEBUG1, (" Reading current reg\n"));
|
||||
int cuurentRegVal = I2C_Read(deviceId, INA226_CURRENT_REG);
|
||||
LOG(logDEBUG1, (" current reg: %d\n", cuurentRegVal));
|
||||
// read it once more as this error has occured once
|
||||
if (cuurentRegVal >= 0xFFF0) {
|
||||
LOG(logDEBUG1, (" Reading current reg again\n"));
|
||||
cuurentRegVal = I2C_Read(deviceId, INA226_CURRENT_REG);
|
||||
LOG(logDEBUG1, (" current reg: %d\n", cuurentRegVal));
|
||||
}
|
||||
|
||||
// should be the same
|
||||
LOG(logDEBUG1, (" ===============current reg: %d, current unit "
|
||||
"cal:%d=================================\n",
|
||||
cuurentRegVal, retval));
|
||||
// current in uA
|
||||
int currentuA = cuurentRegVal * INA226_CURRENT_IMIN_UA;
|
||||
LOG(logDEBUG1, (" current: %d uA\n", currentuA));
|
||||
|
||||
// current in mA
|
||||
int currentmA = (currentuA / 1000.00) + 0.5;
|
||||
LOG(logDEBUG1, (" current: %d mA\n", currentmA));
|
||||
|
||||
LOG(logINFO,
|
||||
("Current via I2C (Device: 0x%x): %d mA\n", deviceId, currentmA));
|
||||
|
||||
return currentmA;
|
||||
}
|
||||
Binary file not shown.
@@ -3,10 +3,10 @@
|
||||
/** API versions */
|
||||
#define APILIB "0.0.0 0x250909"
|
||||
#define APIRECEIVER "0.0.0 0x250822"
|
||||
#define APICTB "0.0.0 0x260421"
|
||||
#define APIGOTTHARD2 "0.0.0 0x260420"
|
||||
#define APIMOENCH "0.0.0 0x260420"
|
||||
#define APIEIGER "0.0.0 0x260420"
|
||||
#define APIXILINXCTB "0.0.0 0x260420"
|
||||
#define APIJUNGFRAU "0.0.0 0x260420"
|
||||
#define APIMYTHEN3 "0.0.0 0x260420"
|
||||
#define APICTB "0.0.0 0x260427"
|
||||
#define APIGOTTHARD2 "0.0.0 0x260427"
|
||||
#define APIMOENCH "0.0.0 0x260424"
|
||||
#define APIEIGER "0.0.0 0x260424"
|
||||
#define APIXILINXCTB "0.0.0 0x260427"
|
||||
#define APIJUNGFRAU "0.0.0 0x260424"
|
||||
#define APIMYTHEN3 "0.0.0 0x260427"
|
||||
|
||||
@@ -31,20 +31,25 @@ PULL_SOCKET_PREFIX_FNAME = LOG_PREFIX_FNAME + '_pull_socket_'
|
||||
SYNCHRONIZER_SUFFIX_FNAME = LOG_PREFIX_FNAME + '_synchronizer.txt'
|
||||
|
||||
|
||||
def startFrameSynchronizerPullSocket(name, fp, quiet_mode=False):
|
||||
def startFrameSynchronizerPullSocket(name, fp, no_log_file = False, quiet_mode=False):
|
||||
cmd = ['python', '-u', 'frameSynchronizerPullSocket.py']
|
||||
fname = PULL_SOCKET_PREFIX_FNAME + name + '.txt'
|
||||
if no_log_file:
|
||||
fname = None
|
||||
startProcessInBackground(cmd, fp, fname, quiet_mode)
|
||||
time.sleep(1)
|
||||
checkLogForErrors(fp, fname)
|
||||
if not no_log_file:
|
||||
checkLogForErrors(fp, fname)
|
||||
|
||||
|
||||
|
||||
def startFrameSynchronizer(num_mods, fp, quiet_mode=False):
|
||||
def startFrameSynchronizer(num_mods, fp, no_log_file = False, quiet_mode=False):
|
||||
cmd = [str(build_dir / 'slsFrameSynchronizer'), str(DEFAULT_TCP_RX_PORTNO), str(num_mods)]
|
||||
# in 10.0.0
|
||||
#cmd = ['slsFrameSynchronizer', '-p', str(DEFAULT_TCP_RX_PORTNO), '-n', str(num_mods)]
|
||||
fname = SYNCHRONIZER_SUFFIX_FNAME
|
||||
if no_log_file:
|
||||
fname = None
|
||||
startProcessInBackground(cmd, fp, fname, quiet_mode)
|
||||
time.sleep(1)
|
||||
|
||||
@@ -105,8 +110,8 @@ def startTestsForAll(args, fp):
|
||||
Log(LogLevel.INFOBLUE, f'Synchronizer Tests for {server}', fp, True)
|
||||
cleanup(fp)
|
||||
startDetectorVirtualServer(server, args.num_mods, fp, args.quiet)
|
||||
startFrameSynchronizerPullSocket(server, fp, args.quiet)
|
||||
startFrameSynchronizer(args.num_mods, f, args.quiet_modep)
|
||||
startFrameSynchronizerPullSocket(server, fp, args.no_log_file, args.quiet)
|
||||
startFrameSynchronizer(args.num_mods, fp, args.no_log_file, args.quiet)
|
||||
d = loadConfig(name=server, rx_hostname=args.rx_hostname, settingsdir=args.settingspath, log_file_fp=fp, num_mods=args.num_mods, num_frames=args.num_frames)
|
||||
loadBasicSettings(name=server, d=d, fp=fp)
|
||||
acquire(fp, d)
|
||||
|
||||
Reference in New Issue
Block a user