change CTB and XCTB clock values to MHz, TODO: units and validation errors

slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c

@@ -66,7 +66,7 @@ uint8_t adcEnableMask_10g = 0xFF;
 uint32_t transceiverMask = DEFAULT_TRANSCEIVER_MASK;
 
 int32_t clkPhase[NUM_CLOCKS] = {};
-uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200};
+uint32_t clkFrequency[NUM_CLOCKS] = {40000000, 20000000, 20000000, 200000000};
 int dacValues[NDAC] = {};
 // software limit that depends on the current chip on the ctb
 int vLimit = 0;
@@ -2119,13 +2119,13 @@ int getMaxPhase(enum CLKINDEX ind) {
         LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind));
         return -1;
     }
-    int ret = ((double)PLL_VCO_FREQ_MHZ / (double)clkFrequency[ind]) *
+    int ret = ((double)PLL_VCO_FREQ_HZ / (double)clkFrequency[ind]) *
               MAX_PHASE_SHIFTS_STEPS;
 
     char *clock_names[] = {CLK_NAMES};
     LOG(logDEBUG1,
-        ("Max Phase Shift (%s): %d (Clock: %d MHz, VCO:%d MHz)\n",
-         clock_names[ind], ret, clkFrequency[ind], PLL_VCO_FREQ_MHZ));
+        ("Max Phase Shift (%s): %d (Clock: %d MHz, VCO:%d Hz)\n",
+         clock_names[ind], ret, clkFrequency[ind], PLL_VCO_FREQ_HZ));
 
     return ret;
 }
@@ -2161,7 +2161,7 @@ int setFrequency(enum CLKINDEX ind, int val) {
         return FAIL;
     }
     char *clock_names[] = {CLK_NAMES};
-    LOG(logINFO, ("\tSetting %s clock (%d) frequency to %d MHz\n",
+    LOG(logINFO, ("\tSetting %s clock (%d) frequency to %d Hz\n",
                   clock_names[ind], ind, val));
 
     // check adc clk too high
@@ -2178,8 +2178,8 @@ int setFrequency(enum CLKINDEX ind, int val) {
 
     // Calculate and set output frequency
     clkFrequency[ind] =
-        ALTERA_PLL_SetOutputFrequency(ind, PLL_VCO_FREQ_MHZ, val);
-    LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind],
+        ALTERA_PLL_SetOutputFrequency(ind, PLL_VCO_FREQ_HZ, val);
+    LOG(logINFO, ("\t%s clock (%d) frequency set to %d Hz\n", clock_names[ind],
                   ind, clkFrequency[ind]));
 
     // phase reset by pll (when setting output frequency)
@@ -2209,12 +2209,12 @@ int getFrequency(enum CLKINDEX ind) {
     }
     #ifndef VIRTUAL
         // get the measured frequency from the firmware
-        int measuredFreqkHz = ALTERA_PLL_getFrequency(ind);
+        int measuredFreqHz = ALTERA_PLL_getFrequency(ind);
 
         // checking against 0 here ensures compatibility with old firmware, TODO: remove this check at some point
-        if (measuredFreqkHz != 0) {
+        if (measuredFreqHz != 0) {
             // Round to nearest MHz. (should we round at all ?)
-            clkFrequency[ind] = (measuredFreqkHz + 500) / 1000;
+            clkFrequency[ind] = measuredFreqHz;
         }
     #endif VIRTUAL
     return clkFrequency[ind];

slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h

@@ -54,7 +54,7 @@
 #define DEFAULT_ADC_CLK               (40)  // 20
 #define DEFAULT_SYNC_CLK              (40)  // 20
 #define DEFAULT_DBIT_CLK              (200)
-#define NS_TO_CLK_CYCLE               (1E-3) // ns to MHz
+#define NS_TO_CLK_CYCLE               (1E-9) // ns to MHz
 #define DEFAULT_TRANSCEIVER_MASK      (0x3)
 
 #define MAX_TRANSCEIVER_MASK    (0xF)
@@ -95,8 +95,8 @@
 #define BIT32_MSK              (0xFFFFFFFF)
 #define BIT16_MASK             (0xFFFF)
 
-#define MAXIMUM_ADC_CLK  (65)
-#define PLL_VCO_FREQ_MHZ (800)
+#define MAXIMUM_ADC_CLK  (65000000)
+#define PLL_VCO_FREQ_HZ (800000000)
 
 /* Struct Definitions */
 typedef struct udp_header_struct {

slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.h

@@ -163,7 +163,6 @@ int setPhase(enum CLKINDEX ind, int val, int degrees);
 int getPhase(enum CLKINDEX ind, int degrees);
 int getMaxPhase(enum CLKINDEX ind);
 int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
-// void       	setFrequency(enum CLKINDEX ind, int val);
 int getFrequency(enum CLKINDEX ind);
 int getVCOFrequency(enum CLKINDEX ind);
 int setReadoutSpeed(int val);

slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.h

@@ -195,7 +195,6 @@ int setPhase(enum CLKINDEX ind, int val, int degrees);
 int getPhase(enum CLKINDEX ind, int degrees);
 int getMaxPhase(enum CLKINDEX ind);
 int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
-// void       	setFrequency(enum CLKINDEX ind, int val);
 int getFrequency(enum CLKINDEX ind);
 int getVCOFrequency(enum CLKINDEX ind);
 int getMaxClockDivider();

slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h

@@ -75,11 +75,11 @@ void ALTERA_PLL_SetModePolling();
 /**
  * Calculate and write output frequency
  * @param clkIndex clock index
- * @param pllVCOFreqMhz PLL VCO Frequency in Mhz
+ * @param pllVCOFreqHz PLL VCO Frequency in Hz
  * @param value frequency to set to
  * @param frequency set
  */
-int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqMhz, int value);
+int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqHz, int value);
 
 /**
  * get measured clock frequency

slsDetectorServers/slsDetectorServer/src/ALTERA_PLL.c

@@ -283,12 +283,12 @@ void ALTERA_PLL_SetModePolling() {
                                  ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
 }
 
-int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
-    LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n",
-                    clkIndex, value, pllVCOFreqMhz));
+int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqHz, int value) {
+    LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dHz)\n",
+                    clkIndex, value, pllVCOFreqHz));
 
     // calculate output frequency, round to next closest integer division
-    uint32_t total_div = (pllVCOFreqMhz + value / 2) / value;
+    uint32_t total_div = (pllVCOFreqHz + value / 2) / value;
 
     // assume 50% duty cycle
     uint32_t low_count = total_div / 2;
@@ -321,7 +321,7 @@ int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
     // as adc clock is stopped temporarily when resetting pll)
     ALTERA_PLL_ResetPLL();
 
-    /*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));
+    /*double temp = ((double)pllVCOFreqHz / (double)(low_count + high_count));
         if ((temp - (int)temp) > 0.0001) {
                 temp += 0.5;
         }
@@ -331,18 +331,14 @@ int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
     #if defined(CHIPTESTBOARDD)
         // wait for firmware to measure the actual frequency
         usleep(2 * 1000 * 1000);
+        value = ALTERA_PLL_getFrequency(clkIndex);
+        LOG(logDEBUG1, ("Frequency is %d\n", value));
     #endif
     return value;
 }
 
 #if defined(CHIPTESTBOARDD)
 uint32_t ALTERA_PLL_getFrequency(uint32_t clk_index) {
-
-    uint32_t base_addr = ALTERA_PLL_FREQ_MEASURE_BASE;
-    uint32_t addr = base_addr + clk_index * 2;
-    uint32_t counter_val = bus_r(addr);
-    // Hz => round to nearest kHz
-    uint32_t freq_kHz = (counter_val + 500) / 1000;
-    return freq_kHz;
+    return bus_r(ALTERA_PLL_FREQ_MEASURE_BASE + clk_index * 2);
 }
 #endif

slsDetectorServers/slsDetectorServer/src/XILINX_PLL.c

@@ -11,9 +11,9 @@
 // leave some things away)
 
 // clang-format off
-#define XILINX_PLL_INPUT_FREQ           (100000) // 100 MHz
-#define XILINX_PLL_MIN_FREQ             (10000)
-#define XILINX_PLL_MAX_FREQ             (250000)
+#define XILINX_PLL_INPUT_FREQ           (100000000) // 100 MHz
+#define XILINX_PLL_MIN_FREQ             (10000000)
+#define XILINX_PLL_MAX_FREQ             (250000000)
 #define XILINX_PLL_MAX_CLK_DIV          (256)
 #define XILINX_PLL_NUM_CLKS             (7)
 #define XILINX_PLL_MAX_NUM_CLKS_FOR_GET (3)
@@ -160,11 +160,7 @@ uint32_t XILINX_PLL_getFrequency(uint32_t clk_index) {
         clk_index -= XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS;
         base_addr = XILINX_PLL_MEASURE_BASE_ADDR1;
     }
-    uint32_t addr = base_addr + clk_index * XILINX_PLL_MEASURE_WIDTH;
-    uint32_t counter_val = bus_r_csp2(addr);
-    // Hz => round to nearest kHz
-    uint32_t freq_kHz = (counter_val + 500) / 1000; // round to nearest kHz
-    return freq_kHz;
+    return bus_r_csp2(base_addr + clk_index * XILINX_PLL_MEASURE_WIDTH);
 }
 
 bool XILINX_PLL_isLocked() {

slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c

@@ -5842,11 +5842,9 @@ int set_clock_frequency(int file_des) {
         case ADC_CLOCK:
             c = ADC_CLK;
             break;
-#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
         case DBIT_CLOCK:
             c = DBIT_CLK;
             break;
-#endif
         case RUN_CLOCK:
             c = RUN_CLK;
             break;
@@ -5867,26 +5865,19 @@ int set_clock_frequency(int file_des) {
                     (int)c);
 
             if (getFrequency(c) == val) {
-                LOG(logINFO, ("Same %s: %d %s\n", modeName, val,
-                              myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
+                LOG(logINFO, ("Same %s: %d %s\n", modeName, val, "Hz"));
             } else {
-                int ret = setFrequency(c, val);
+                int ret = setFrequency(c, val); // MM: Poblem
                 if (ret == FAIL) {
-                    sprintf(mess, "Could not set %s to %d %s\n", modeName, val,
-                            myDetectorType == XILINX_CHIPTESTBOARD ? "kHz"
-                                                                   : "MHz");
+                    sprintf(mess, "Could not set %s to %d %s\n", modeName, val,"Hz");
                     LOG(logERROR, (mess));
                 } else {
                     int retval = getFrequency(c);
                     LOG(logDEBUG1,
-                        ("retval %s: %d %s\n", modeName, retval,
-                         myDetectorType == XILINX_CHIPTESTBOARD ? "kHz"
-                                                                : "MHz"));
-#if !defined(XILINX_CHIPTESTBOARDD) && !defined(CHIPTESTBOARDD)
+                        ("retval %s: %d %s\n", modeName, retval, "Hz"));
                     // both CTB's will give the actual frequency, which is not
                     // 100% identical to the set frequency
                     validate(&ret, mess, val, retval, modeName, DEC);
-#endif
                 }
             }
         }

slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorServer_defs.h

@@ -163,4 +163,4 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
 #define DEFAULT_ADC_CLK  (100000) // 100 MHz
 #define DEFAULT_SYNC_CLK (20000)  // 20 MHz
 #define DEFAULT_DBIT_CLK (100000) // 100 MHz
-#define NS_TO_CLK_CYCLE  (1E-6)   // ns to kHz
+#define NS_TO_CLK_CYCLE  (1E-9)   // ns to Hz