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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-08-09 06:40:29 +02:00
update default values in server defs
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@@ -66,7 +66,7 @@ uint8_t adcEnableMask_10g = 0xFF;
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uint32_t transceiverMask = DEFAULT_TRANSCEIVER_MASK;
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int32_t clkPhase[NUM_CLOCKS] = {};
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uint32_t clkFrequency[NUM_CLOCKS] = {40000000, 20000000, 20000000, 200000000};
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uint32_t clkFrequency[NUM_CLOCKS] = {DEFAULT_RUN_CLK, DEFAULT_ADC_CLK, DEFAULT_SYNC_CLK, DEFAULT_DBIT_CLK};
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int dacValues[NDAC] = {};
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// software limit that depends on the current chip on the ctb
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int vLimit = 0;
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@@ -50,10 +50,10 @@
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#define DEFAULT_VLIMIT (-100)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_RUN_CLK (200) // 40
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#define DEFAULT_ADC_CLK (40) // 20
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#define DEFAULT_SYNC_CLK (40) // 20
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#define DEFAULT_DBIT_CLK (200)
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#define DEFAULT_RUN_CLK (80000000) // 80
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#define DEFAULT_ADC_CLK (40000000) // 40
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#define DEFAULT_SYNC_CLK (40000000) // 40
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#define DEFAULT_DBIT_CLK (200000000)
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#define NS_TO_CLK_CYCLE (1E-9) // ns to MHz
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#define DEFAULT_TRANSCEIVER_MASK (0x3)
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@@ -5931,13 +5931,7 @@ int get_clock_frequency(int file_des) {
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retval = getFrequency(c);
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char *clock_names[] = {CLK_NAMES};
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LOG(logDEBUG1,
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("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c,
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retval,
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myDetectorType == XILINX_CHIPTESTBOARD
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? "kHz"
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: (myDetectorType == GOTTHARD2 || myDetectorType == MYTHEN3
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? "Hz"
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: "MHz")));
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("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c, retval, "Hz"));
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}
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#endif
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return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
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