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update registerDefs.h
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muelle_m1
2026-01-05 09:31:32 +01:00
parent 8063560e3a
commit dece2e16b4
1 changed files with 49 additions and 0 deletions
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49
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
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@@ -339,6 +339,8 @@
#define READOUTFROMASIC_OFST (4)
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
#define MISO_SELECT (0xC018)
#define TRANSCEIVERRXCTRL0REG1 (0xC100)
#define TRANSCEIVERRXCTRL0REG2 (0xC104)
@@ -401,6 +403,12 @@
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define RXWORDALIGNINVERT_OFST (17)
#define RXWORDALIGNINVERT_MSK (0x0000000f << RXWORDALIGNINVERT_OFST)
#define ENABLEDVALIDLOCK_OFST (21)
#define ENABLEDVALIDLOCK_MSK (0x00000001 << ENABLEDVALIDLOCK_OFST)
#define ENABLEMANUALWORDALIGN_OFST (22)
#define ENABLEMANUALWORDALIGN_MSK (0x00000001 << ENABLEMANUALWORDALIGN_OFST)
#define TRANSCEIVERERRCNT_REG0 (0xC124)
@@ -450,6 +458,47 @@
#define RXDATACH3_OFST (0)
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
#define PATTERN_BYPASS (0xC200)
#define PATTERN_BYPASS_ENABLE (0xC204)
#define PATTERN_MOSI_BITSELECT (0xC208)
#define PATTERN_SCLK_BITSELECT (0xC20C)
#define PATTERN_SPI_WRITEDATA (0xC210)
#define PATTERN_MUX_CTRL (0xC214)
#define SPI_FULL_OFST (1)
#define SPI_FULL_MSK (0x00000001 << SPI_FULL_OFST)
#define MISO_FIFO_CLEAR_OFST (2)
#define MISO_FIFO_CLEAR_MSK (0x00000001 << MISO_FIFO_CLEAR_OFST)
#define MISO_FIFO_FULL_OFST (3)
#define MISO_FIFO_FULL_MSK (0x00000001 << MISO_FIFO_FULL_OFST)
#define MISO_FIFO_EMPTY_OFST (4)
#define MISO_FIFO_EMPTY_MSK (0x00000001 << MISO_FIFO_EMPTY_OFST)
#define ENABLE_CPU_SPI_OFST (5)
#define ENABLE_CPU_SPI_MSK (0x00000001 << ENABLE_CPU_SPI_OFST)
#define SPI_REVERSE_BITORDER_OFST (6)
#define SPI_REVERSE_BITORDER_MSK (0x00000001 << SPI_REVERSE_BITORDER_OFST)
#define MISO_DATA (0xC218)
#define PATTERN_CSN_BITSELECT (0xC21C)
#define SPI_NBITS (0xC220)
#define SPI_NBITS_OFST (0)
#define SPI_NBITS_MSK (0x0000001f << SPI_NBITS_OFST)
#define DATAGEN_CTRL (0xC300)
#define DATAGEN_MH1_ENABLE_OFST (0)
#define DATAGEN_MH1_ENABLE_MSK (0x00000001 << DATAGEN_MH1_ENABLE_OFST)
#define DATAGEN_MH1_RESETN_OFST (1)
#define DATAGEN_MH1_RESETN_MSK (0x00000001 << DATAGEN_MH1_RESETN_OFST)
// ----------------------------------------------------
// TODO: fix these in the firmware reg generator: