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round CTB clocks to next closest possible value, added freq measurement

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muelle_m1
2026-03-11 17:57:20 +01:00
parent c86ca1eaec
commit f9b3c4f9ce
5 changed files with 51 additions and 7 deletions
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slsDetectorServers/ctbDetectorServer/RegisterDefs.h
+3
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@@ -628,6 +628,9 @@
#define ADC_SLOW_CTRL_DONE_OFST (1)
#define ADC_SLOW_CTRL_DONE_MSK (0x00000001 << ADC_SLOW_CTRL_DONE_OFST)
/* Clock Measurement base reg */
#define PLL_FREQ_MEASURE_REG (0x44 << MEM_MAP_SHIFT)
/** I2C Control register */
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
BIN
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Binary file not shown.
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
+6 -2
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@@ -554,7 +554,7 @@ void setupDetector() {
ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG,
PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK,
PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK,
PLL_CNTRL_ADDR_OFST);
PLL_CNTRL_ADDR_OFST, PLL_FREQ_MEASURE_REG);
ALTERA_PLL_ResetPLLAndReconfiguration();
resetCore();
@@ -2179,7 +2179,7 @@ int setFrequency(enum CLKINDEX ind, int val) {
// Calculate and set output frequency
clkFrequency[ind] =
ALTERA_PLL_SetOuputFrequency(ind, PLL_VCO_FREQ_MHZ, val);
ALTERA_PLL_SetOutputFrequency(ind, PLL_VCO_FREQ_MHZ, val);
LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind],
ind, clkFrequency[ind]));
@@ -2208,6 +2208,10 @@ int getFrequency(enum CLKINDEX ind) {
LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind));
return -1;
}
#ifndef VIRTUAL
// get the measured frequency from the firmware, round to next closest MHz (should we round at all ?)
clkFrequency[ind] = (ALTERA_PLL_getFrequency(ind) + 500) / 1000;
#endif VIRTUAL
return clkFrequency[ind];
}
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h
+12 -1
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@@ -20,6 +20,10 @@
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index);
#elif defined(CHIPTESTBOARDD)
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t freqreg);
#else
/**
* Set Defines
@@ -75,4 +79,11 @@ void ALTERA_PLL_SetModePolling();
* @param value frequency to set to
* @param frequency set
*/
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);
int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqMhz, int value);
/**
* get measured clock frequency
*/
#if defined(CHIPTESTBOARDD)
uint32_t ALTERA_PLL_getFrequency(uint32_t clkIDX);
#endif
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL.c
+30 -4
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@@ -130,7 +130,8 @@ uint32_t ALTERA_PLL_Cntrl_WrPrmtrMask = 0x0;
#if defined(JUNGFRAUD)
uint32_t ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask = 0x0;
int ALTERA_PLL_Cntrl_DBIT_ClkIndex = 0;
#elif defined(CHIPTESTBOARDD)
uint32_t ALTERA_PLL_FREQ_MEASURE_BASE = 0x0;
#endif
uint32_t ALTERA_PLL_Cntrl_PLLRstMask = 0x0;
uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
@@ -150,6 +151,19 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask = wd2msk;
ALTERA_PLL_Cntrl_DBIT_ClkIndex = clk2Index;
}
#elif defined(CHIPTESTBOARDD)
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t freqreg) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
ALTERA_PLL_Cntrl_WrPrmtrMask = wpmsk;
ALTERA_PLL_Cntrl_PLLRstMask = prmsk;
ALTERA_PLL_Cntrl_AddrMask = amsk;
ALTERA_PLL_Cntrl_AddrOfst = aofst;
ALTERA_PLL_FREQ_MEASURE_BASE = freqreg;
}
#else
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
@@ -269,12 +283,12 @@ void ALTERA_PLL_SetModePolling() {
ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
}
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n",
clkIndex, value, pllVCOFreqMhz));
// calculate output frequency
uint32_t total_div = (float)pllVCOFreqMhz / (float)value;
// calculate output frequency, round to next closest integer division
uint32_t total_div = (pllVCOFreqMhz + value / 2) / value;
// assume 50% duty cycle
uint32_t low_count = total_div / 2;
@@ -315,3 +329,15 @@ int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
*/
return value;
}
#if defined(CHIPTESTBOARDD)
uint32_t ALTERA_PLL_getFrequency(uint32_t clk_index) {
uint32_t base_addr = ALTERA_PLL_FREQ_MEASURE_BASE;
uint32_t addr = base_addr + clk_index * 2;
uint32_t counter_val = bus_r(addr);
// Hz => round to nearest kHz
uint32_t freq_kHz = (counter_val + 500) / 1000;
return freq_kHz;
}
#endif