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c86bc4591c
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AcquisitionDevice: Remove automatic setup of radial integration
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2023-10-21 16:08:49 +02:00 |
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4ede0f1f15
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FPGA: rename axis_256_to_512.cpp file
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2023-10-21 15:38:40 +02:00 |
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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d91eb6bdd5
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FPGAIntegrationTest: Use multiple modules
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2023-10-21 11:08:07 +02:00 |
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0b5bbec1fc
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AcquisitionDevice: Setup rad. int. mapping automatically
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2023-10-20 18:00:29 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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a338a1743b
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RawToConvertedGeometry: Add function to calculate location of a raw pixel in converted geometry
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2023-10-20 13:27:21 +02:00 |
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ad78fb0149
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FPGA: Fixes and simplifications to spot_finder core + SNR threshold test
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2023-10-20 12:23:50 +02:00 |
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4e4a232a6d
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Definitions: Increase max gRPC message size to 2 GB -> need to change later how calibration is being transferred
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2023-10-20 11:40:09 +02:00 |
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45de356c16
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FPGA: Minor changes
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2023-10-19 22:43:35 +02:00 |
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aa1ff0436b
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FPGA: Add SNR threshold to spot finder
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2023-10-19 22:29:38 +02:00 |
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60466fe146
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FPGA: Add extra comment to spot_finder
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2023-10-19 20:56:24 +02:00 |
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9f48e4b317
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FPGA: remove spot_finder.h
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2023-10-19 20:53:38 +02:00 |
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f04f7a274b
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FPGA: Name spot finder signals in consistent manner
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2023-10-19 20:52:09 +02:00 |
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67b9e08a5c
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FPGAIntegrationTest: Add test for spot finder based on count limit
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2023-10-19 19:48:40 +02:00 |
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90344eb251
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FPGA: Basic spot finder (i.e. only based on count threshold) as a placeholder
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2023-10-19 19:40:31 +02:00 |
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c7b7abb34d
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FPGA: Remove register slice for strong pixel result
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2023-10-19 12:14:17 +02:00 |
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6691b01265
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PCIe driver: accept spot finding parameters
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2023-10-18 21:23:41 +02:00 |
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a56a54c72d
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AcquisitionDevice: GetDeviceOutput to get the whole package
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2023-10-18 19:42:57 +02:00 |
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6f9f918ee6
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HLS: Improve make scripts, so HLS test bench can be defined
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2023-10-18 16:32:31 +02:00 |
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736a181e5e
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HLS: Spot finder outputs parameters + statistics
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2023-10-18 15:19:01 +02:00 |
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ec7278bd44
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HLS: Changes to allow cosimulation with Vitis HLS
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2023-10-18 14:44:30 +02:00 |
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e4ac3e8b08
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FPGASpotFindingUnitTest: Very basic test for spot finder
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2023-10-18 12:10:29 +02:00 |
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6565619035
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parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS)
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2023-10-18 12:10:00 +02:00 |
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79df7cf7d5
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FPGA: Add extra AXI-Stream register slices
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2023-10-17 19:40:55 +02:00 |
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83fb1fd465
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FPGA: Clean-up of prefix_sum
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2023-10-17 13:22:49 +02:00 |
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217992be94
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FPGA: Second variant of prefix sum
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2023-10-17 10:39:11 +02:00 |
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05338887a7
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FPGA: Spot finder accepts 16-bit number for strong pixel threshold
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2023-10-16 22:07:41 +02:00 |
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faca7a3f15
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PCIe driver: Clean-up + add intermediate library between driver and AcquisitionDevice
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2023-10-16 19:54:13 +02:00 |
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2fd8d38782
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PCIe driver: add basic permission handling
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2023-10-16 15:13:47 +02:00 |
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202b7ee0ca
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PCIe driver: clean-up
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2023-10-16 15:13:47 +02:00 |
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c5ca10792e
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FPGA: Clean-up of spot_finder core + update README.MD
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2023-10-16 15:13:47 +02:00 |
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9b646a4195
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FPGA: Spot finder 2nd version more improved
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2023-10-04 16:59:13 +02:00 |
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7889f1666a
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FPGA: Spot finder 2nd version improved
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2023-10-04 12:12:43 +02:00 |
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5460c10f76
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FPGA: Spot finder 2nd version
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2023-10-03 22:14:11 +02:00 |
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81c1502d52
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FPGA: Added spot_finder_line_sum (work in progress)
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2023-10-03 18:51:26 +02:00 |
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f301923c72
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FPGA: Added spot_finder_update_sum function, as first step for versatile spot finder
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2023-10-03 14:28:39 +02:00 |
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c6afbebd13
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FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result)
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2023-10-02 22:34:49 +02:00 |
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98fe70315b
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FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design)
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2023-09-30 11:28:01 +02:00 |
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59d0850b1f
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:08:55 +02:00 |
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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8831ad380f
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FPGA: Fix bug in adu_histo + add test + add access from AcquisitionDevice
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2023-09-29 18:34:29 +02:00 |
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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5bb92aed61
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FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer
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2023-09-29 14:44:08 +02:00 |
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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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0f7c14c267
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FPGA: integration calculates sum^2
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2023-09-25 22:23:06 +02:00 |
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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027b3aa943
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Revert "FPGA: add register slices"
This reverts commit cf2163a402.
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2023-09-25 21:52:54 +02:00 |
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4028a59c4a
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PCIe driver: add option to read/write register
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2023-09-24 22:58:16 +02:00 |
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