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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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8dcecb9685
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Add deep learning resolution estimation model from Stanford
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2024-02-08 20:15:29 +01:00 |
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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d82bd13917
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Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
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2023-12-14 22:39:17 +01:00 |
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0b69dfb290
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New REST+OpenAPI interface
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2023-12-11 12:11:54 +01:00 |
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f1935526a7
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Generalized serializer
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2023-12-11 06:49:24 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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d2f1c569a7
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FPGA: Modify FPGA register map (move action configuration to offset 0x200)
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2023-11-21 15:24:55 +01:00 |
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8635724ca3
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Move FPGA register map from Definitions.h to jfjoch_drv.h
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2023-11-21 15:20:12 +01:00 |
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1e6f64b4da
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FPGA: Increase max summation to 256
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2023-11-16 21:32:37 +01:00 |
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0d3cb19a2e
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Fix tests + trim unnecessary variables in DataProcessingSettings
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2023-11-16 19:58:24 +01:00 |
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4307a670eb
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gRPC is necessary only for JFJochBroker
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2023-11-16 18:47:53 +01:00 |
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bb8e0f7b84
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Fix unnecessary JSON <-> gRPC headers
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2023-11-15 21:24:42 +01:00 |
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3f7fc04d84
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Monolithic design achieved! (jfjoch_broker is NOT up to date!)
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2023-11-14 18:23:43 +01:00 |
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2b6901af58
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DiffractionExperiment: Move DetectorSettings and DatasetSettings to JFJochStateMachine
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2023-11-14 16:33:19 +01:00 |
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f778a35e6f
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DiffractionExperiment: Move internal variables to a C++ structure
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2023-11-14 13:17:58 +01:00 |
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e85988dfa2
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DiffractionExperiment: Clean-up Compression and UnitCell
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2023-11-13 17:06:34 +01:00 |
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dbef6a3b17
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JFJochReceiver is directly invoked by the broker
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2023-11-13 16:08:28 +01:00 |
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b270b8857a
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TestImagePusher: Increase tolerance for conversion errors in summation
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2023-11-12 13:32:44 +01:00 |
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834d8e8dcd
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ADUHistogram: Fix return missing
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2023-11-11 22:43:15 +01:00 |
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eaf7792459
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DataProcessingSettings has equivalent C++ and ProtoBuf structures
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2023-11-11 18:48:38 +01:00 |
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d83b8d465d
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JFJochReceiver: Plot is C++ struct
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2023-11-10 21:22:42 +01:00 |
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04c251d16a
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gRPC: Remove optional variables from ProtoBuf
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2023-11-10 17:43:51 +01:00 |
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4efcdaab74
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AcqusitionDevice: Moved to dedicated directory
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2023-11-10 11:45:16 +01:00 |
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7993efb047
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DetectorSettings: remove optional fields
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2023-11-09 20:51:37 +01:00 |
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56476e3e5f
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ZMQPreviewPublisher: Stream CBOR data
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2023-11-08 19:19:32 +01:00 |
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98cb58d199
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PCIe driver: Fix addresses for calibration and frame generator
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2023-11-08 14:36:36 +01:00 |
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41985b6c29
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FPGA: Increase data width of conversion to 18-bit. This allows to use full unsigned precision + raw data are handled properly.
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2023-11-07 19:11:37 +01:00 |
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2dfd878d01
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JFConversionFloatingPoint: Integrate other bit depths/signs
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2023-11-07 15:36:49 +01:00 |
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de317c29d5
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JFConversion: Clean-up
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2023-11-07 13:28:27 +01:00 |
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310d77a57f
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JFJochReceiver: No access to preview frame via gRPC
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2023-11-07 10:13:19 +01:00 |
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552597523d
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ImagePusher: Serialization of StartMessage is handled outside of the class
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2023-11-06 20:21:27 +01:00 |
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591e724cf6
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DiffractionExperiment: Rename GetFPGAOutputDepth -> GetPixelDepth and GetFPGASummation -> GetSummation
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2023-11-06 18:01:53 +01:00 |
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dec3eb15de
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FrameTransformation: Add two tests for int32 and uint16
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2023-11-06 17:43:14 +01:00 |
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d6c1b19599
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DiffractionExperiment: Remove ROI-mask function
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2023-11-06 16:51:34 +01:00 |
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b2743072e6
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DiffractionExperiment: Remove frame summation (summation only on FPGA)
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2023-11-06 16:09:08 +01:00 |
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fcd7612656
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DiffractionExperiment: Remove 2x2 binning to simplify transformation code
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2023-11-06 14:16:15 +01:00 |
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e6442f6384
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ZMQPreviewPublisher: Support both 16-bit and 32-bit images in preview
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2023-11-03 17:38:23 +01:00 |
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50556932fb
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DiffractionExperiment: Remove spot finder stride
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2023-11-03 16:56:50 +01:00 |
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3d7c7b0779
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Implement FPGA summation
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2023-11-02 20:41:37 +01:00 |
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f21f226a59
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Move MAX_FPGA_SUMMATION to Definitions.h
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2023-11-02 12:55:52 +01:00 |
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b3eceef7cd
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FPGA: Max module number is 32
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2023-11-01 15:55:06 +01:00 |
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112a62fc7f
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FPGA: remove limit of modules for frame_generator
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2023-11-01 14:20:43 +01:00 |
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3940f067a8
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MAX_MODULES_FPGA moved to Definitions.h => This needs to be const for RELEASE_LEVEL
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2023-11-01 13:16:22 +01:00 |
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270dd1224b
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Receiver: remove JF conversion on CPU
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2023-10-28 17:00:04 +02:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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2268486824
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HLS: Added frame_summation core
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2023-10-26 22:31:09 +02:00 |
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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e195432aea
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RawToConvertedGeometry: Separate core functions that require minimum headers
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2023-10-24 17:54:14 +02:00 |
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