Commit Graph

9547 Commits

Author SHA1 Message Date
maliakal_d d1106fec41 Merge branch 'developer' into dev/ctb_clocks
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2026-04-22 16:36:13 +02:00
mazzol_a 973bd89ca5 updated documentation workflow (#1436)
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2026-04-21 11:56:19 +02:00
maliakal_d c05d5a37cd dev/ fix vchip and binaries (#1435)
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* updated binaries and fixed a warning by moving the usleep_bf to blackfin.c

* suppressed warnings

* cleaned up docs

* renamed function

---------

Co-authored-by: Alice <alice.mazzoleni@psi.ch>
2026-04-21 10:59:05 +02:00
Martin Mueller 326df1de97 fix pyctbgui powerindex (#1433)
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* fix pyctbgui powerindex

* detangled power enable and power dac values

* displaybox for vchip

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2026-04-17 09:25:40 +02:00
Martin Mueller 78edfe3b55 Running Matterhorn on altera CTB (#1427)
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* testing matterhorn1 SPI on altera CTB, works for dummy-chip

* added bf_usleep with proper timing for blackfin

* simplified spi firmware interface, removed write and readstrobe

* define constant for BFIN spi sleep

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
2026-04-15 16:23:04 +02:00
maliakal_d 5ec5d46c48 Dev/ctb separate dac and power (#1420)
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* not allowing power names for dac names to prevent duplicate names

* wip

* v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power

* binary in

* dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands

* wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested

* wip. client and xilinx todo

* wip: ctb power works, tests left

* fixed some tests

* added vchip check

* python cmds still left. wip

* fixed xilinx. python left

* wip

* wip. xilinx

* fixed powerchip for ctb

* power all returns all

* configtransceiver is removed

* wip python

* wip

* wip

* wip

* wip

* wip

* wip

* wip xilinx

* wip

* wip

* wip

* pybindings

* fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector

* wip

* fixed tests

* fixes for python api

* wip

* python: moved powerlist to Ctb

* fixed tests to work for powelist in Ctb

* moved signallist, adclist, slowadc, slowadclist to Ctb

* throw approperiate error when no modules added for powers

* added dac test

* fix dac default names and test for dacs

* ctb dacs, yet to do othe rdacs

* dacs should work now even in tests

* run all tests

* DetectorPowers->NamedPowers in ctb

* comments

* removed unnecessary test code

* removed hard coded dac names in python NamedDacs and NamedPowers

* minor

* minor

* fixed error messages

* changed power to  be able to set DAC directly, using enable and disable methods with enabled to get
2026-04-15 10:33:01 +02:00
muelle_m1 2372f93dd9 update help and comments
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2026-03-19 15:23:50 +01:00
muelle_m1 614b5c56d9 change python and pyctbgui to accept and return floating point MHz
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2026-03-19 15:10:03 +01:00
muelle_m1 6811bb1f33 added virtual check in Altera_PLL, update testcases
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2026-03-19 11:49:47 +01:00
muelle_m1 0415911279 update default values in server defs
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2026-03-19 11:30:40 +01:00
muelle_m1 27ea49c8e8 added tolerance to exptime, fixed test
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2026-03-18 17:50:55 +01:00
muelle_m1 a810ddeaf4 do the same for dbit and adcclk
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2026-03-18 15:50:18 +01:00
muelle_m1 339b96cdd3 changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ? 2026-03-18 15:28:16 +01:00
muelle_m1 fc1f4b4a6a change CTB and XCTB clock values to MHz, TODO: units and validation errors
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2026-03-18 14:02:36 +01:00
muelle_m1 e2cb75c27d Merge remote-tracking branch 'origin/developer' into dev/ctb_clocks
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2026-03-18 10:05:51 +01:00
maliakal_d 4ee61ae791 ctb and xilinx: setting all dacs (normal, not power dacs) to 0 (not power down) at startup. This is safer than power down for 4 normal dacs. xilinx ctb: remove disable fmc at power off chip so one can power on and off the chip on their own (#1424)
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2026-03-17 16:53:33 +01:00
muelle_m1 6b13336c95 add check for backwards compatibility
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2026-03-12 15:31:30 +01:00
muelle_m1 778b497eb1 added time for firmware to measrue actual value after frequency change
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2026-03-12 15:13:52 +01:00
muelle_m1 f9b3c4f9ce round CTB clocks to next closest possible value, added freq measurement 2026-03-11 17:57:20 +01:00
mazzol_a c86ca1eaec per default pyqtgraph should read array as row-major (#1419)
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* per default pyqtgraph should read array as row-major

* dont transform for analog images

* never flip rows
2026-03-11 12:28:42 +01:00
maliakal_d 3846aec46e Dev/jungfrau 1m root display support (#1364)
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* Aldo Mozzanica added support for 2 modules in 1M configuration for root display

* deleted the wrong files
2026-03-05 17:13:38 +01:00
maliakal_d 6982b8cfa4 rm unnecessary hidden test tags (#1415)
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* removed hidden tags other than .detectorintegration and .disable_check_data_file

* updated label, minor
2026-03-05 17:11:56 +01:00
maliakal_d 384b2480ab Dev/fix no rx roi port (#1372)
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* rx_roi fixed when there is no roi for a particular port. Fixed tests for it

* removing todo check if files created because its not enough to count matching pattern file names, but also look at timestamp and create files with timestamp else you read older ones. For now, checking individual rois is enough

* restore md5

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2026-03-05 12:28:57 +01:00
Erik Fröjdh a1b8dccdd9 added support for int() for RegisterAddress and RegisterValue (#1414)
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2026-03-05 11:35:21 +01:00
Erik Fröjdh 9f72688b9c Adding offset to RegisterAddress (#1413)
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* implemented + and += for RegisterAddres and tests plus test cleanup
2026-03-05 09:32:21 +01:00
mazzol_a 6e090dbba2 Dev/update workflows (#1406)
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* only run tests for pull-requests

* build gui and simulators

* trigger upon push to all branches

* renamed workflows

* added python tests

* added colorama and numpy

* added slsdet to pythonpath

* updated workflow name
2026-03-02 14:30:27 +01:00
maliakal_d 60f5db1224 xilinx: slow adcs (#1405)
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* xilinx: slow adcs

* minor

* xilinx: max reference voltage back to 2500mV for slow adcs ad7689
2026-02-27 17:17:11 +01:00
maliakal_d a3e6cc90ea server versions werent getting updated (#1407) 2026-02-27 17:12:27 +01:00
maliakal_d a1c5bf971f ctb: vchip doesnt validate with vlimit anymore (#1404)
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2026-02-26 14:22:46 +01:00
mazzol_a 6a9eac17c8 removed make for the pyctbgui (#1401)
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2026-02-25 16:40:32 +01:00
maliakal_d e5b8e4ee80 fix the master hdf5 extension from aprevious PR (#1399)
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2026-02-24 10:49:11 +01:00
maliakal_d 8f07d2a464 Dev/xilinx set dac rewrite (#1389)
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* wip

* wip

* wip. xilinx left

* wip. xilinx

* wip

* wip. compiles

* fixed eiger test

* more fixes

* fixed virtual m3

* fix typos and bugs

* setting power to 0

* set power fixed

* updated server binaries

* minor

* refactoring

* get vchip refactoring

* eiger: unnecessary check for setsettings undefined

* retval pointer for printout

* eiger.wip, mV in boolean

* wip. gotthard2 and m3

* wip. jungfrau

* moench.wip

* compiles.wip

* fix eiger

* m3 fix vthresh

* fix ctband xilinx

* default pwr index = pwr_io

* minor:fn name and highvoltage to local var

* refactor funcs

* minor

* minor

* check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1

* minor

* updated versioning

* review changes: removing validateDACValue and other minor stuff

* binaries in

* wip

* refactored m3 vth

* minor review

* minor review

* m3 serverdac index fix

* minor
2026-02-23 14:23:13 +01:00
mazzol_a f4658ab094 Dev/automate documentation build (#1357)
* some test about building docs

* indendation error

* typo -

* forgot to get package hdf5

* had to add shinx and doxygen as well

* oke created environmnet file

* typo

* dont use conda

* dont use conda

* cannot upload artefact commit to gh-pages

* correct copy

* mmh

* try with tokem

* set write permisison

* script to update main_index for versioned documentation

* rename main_index to index

* use absolute path in python script

* update main_index upon a release

* extract release type from version

* copy release notes

* updated links from devdoc to slsDetectorPackage, handling .md for new versions

* changed page source

* updated documentation link in README

* add guideline for Package Versioning to documentation also used as a test

* typo in workflow

* why didnt it copy?

* copied from build instead of docs

* change back - trigger for push

* only trigger for pull_requests and releases

* removed conda environment file

* automatically update documentation paths in release notes

* only keep templated README.md

* added README and updated links

* update Release notes template manually

* generate release notes script not needed anymore

* modified readme to reflect dependencies insides build from source

* subheadings in dependencies

---------

Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2026-02-23 14:21:44 +01:00
mazzol_a f8723eb0d8 Dev/use aare in pyctbgui (#1379)
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* added CMakeLists.txt for pyctbgui

* using aare decoders

* removed c code

* showing proper error message

* dvjgj

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2026-02-23 12:33:10 +01:00
mazzol_a 65c8f2c7d8 dev/handes trailing / in filepath (#1391)
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* member filePath in Implementation is std::filesystem::path, some refactoring

* PR Review

* adapted function signature - compiled with hdf5 on
2026-02-17 17:11:33 +01:00
muelle_m1 26729b06cb added copy of ctbDetectorServer to auto-deploy
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2026-02-10 16:14:01 +01:00
maliakal_d 1c44a66964 formatted 2026-02-10 16:10:51 +01:00
mazzol_a 1c18803dc9 Merge pull request #1385 from slsdetectorgroup/dev/fix_update_ctb
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skip if not plotted
2026-02-09 15:22:16 +01:00
mazzol_a b3f5473385 Merge branch 'developer' into dev/fix_update_ctb
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2026-02-09 15:17:02 +01:00
Erik Fröjdh 3f4df445f1 send back the result of the SPI write (#1387)
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2026-02-09 13:50:35 +01:00
mazzol_a ec6a8b6d66 added range update
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2026-02-09 12:42:35 +01:00
mazzol_a 78044b2783 always write all wave data & uncheck plot if digital bit unchecked
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2026-02-06 16:41:04 +01:00
mazzol_a 7f5b26743f uff introduced another bug 2026-02-06 14:55:18 +01:00
mazzol_a 92da709bda skip if not plotted 2026-02-06 14:39:11 +01:00
Erik Fröjdh 0992c7ae4c Read and write SPI for Xilinx CTB (#1381)
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-readSpi and writeSpi in C++ and Python API
2026-02-05 17:20:47 +01:00
muelle_m1 fb58fefe57 added RegDefs for 1G support on XCTB
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2026-02-05 15:11:31 +01:00
mazzol_a 28b2aa9673 Dev/add simulator tests in GitHub workflows (#1337)
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* added simulator tests in github workflows

* indentation error

* typo

* debug

* Logging for debugging

* added more debug lines

* more debugging

* debug

* debug

* debug

* dont throw if process does not exist

* debug

* added absolute path to sls_detector commands

* some refactoring in test scripts

* added absolute path to all slsdet command

* typo

* ../tests/scripts/test_frame_synchronizer.py

* raise exception upon failure for github workflows

* removed hidden tags

* some refactoring in test scripts

* some refactoring

* fixed CMakeLists

* fixed unsuccesful merge

* updated python tests using simulators

* debug import error

* debug module import

* python -m runs module pytest as script - everything in path available

* removed integartion tests

* enable file write not to log files

* run tests without log files

* increased sleep time for udp packets

* added logg level variable to cmake

* added testing policies to documenattion

* disabled check for num_frames for jungfrau & xilinx

* set log level as cmake cached variable

* disable tests for jungfrau and xilinx_ctb

* check frames for HDF5

* updated Documentation of Testing

* changed withdetectorsimulators to detectorintegration

* replaced [.cmdcall] with [.detectorintegration]

* check_file_size only disabled for jungfrau - disable for all roi tests

* changed time to wait after receive to 5 ms

* take into account half modules of eiger

* num udp interfaces needs to be consistent across modules

* suppressed warning enclosing if

* config added 2 udp ports per default for moench and jungfrau

* write detector output to console

* allow jungfrau to tests num frames, remove unused variable (numinterfaces), add comment for future to handle traceback to know which calling function threw the files unmatched, added documentation for tests (examples for .detectoritnegration and how to disable marked tests, removed addditional argumetns to disable for test_simulator as one can just use ~, removed the check that checks for jungfrau checking number of frames at master attributes and at rx test, removed unused advanced_test_settings in test_simulator script, the num_mods check for multiple modules is removed and default num  modules set to 1 for test_simulator (to be increased later), back to raising exception for killprocess

* removed integration tests from cmakelists.txt and cmk.sh, modified the tests workflow command to reflect the disable argument and removed xilinx_ctb from test (fix fromdeveloper merge to be done)

* filtering by actual name for disable certain tests on github workflow

* minor refactor

* wip

* wip

* changes to run on local rh9 runner instead of github workfloa

* modified yml to remove some leftover from github workflow

* test

* fix build_dir in scripts (github workflow) and pytest dir in gitea workflow

* making the local machine use python3.13 binary

* pythonpath added

* changes for build_Dir back

* allowing ctb api tests

* allowed ctb api tests and set up slsdetname envt variable for shared memory being reserved just for these tests

* added rh8 workflow for local runner on gitea

* remnants from rh9 local runner

* remnants from rh9 local runner

* conda env for all shell for local runner

* allowing hdf5 to build on local runner

* run all tests for both the runners

* refactored fixtures a bit and merged some tests that use one session for entire server

* test fail

* test fix

* adding github workflow to test without data file checks and without logs

* documentation changes

* unnecessary import in conftest

* allowing the session_simulator to test for multiple modules and interfaces etc

* allow test_simulator script to run for 2 modules for all modules except ctb and xilinx ctb

* run upon push

* removing the disable file check on github workflow

* minor adjustment

* testing without synch

* reverting to previous

* with log file

* without the space

* summary from file and more error extracts from file to terminal

* minor

* trying nlf for more details

* updated with no log file to print everything to screen  also for det and rxr

* trying a no throw

* stoi was more about indent in yaml

* tries

* wip

* debug

* number of frames inconsistent fix=>just take first one, only test xilinx

* jungfrau tests without frames caught check

* extend the disable file check to everywhere that creates files

* specify path for test_simulator

* withoutprinting ==

* wip

* back with printing===, but not parsing file for errors anymore

* lang?

* wip

* safe log?

* wip2

* wip

* dont split error as its streaming live, just raise

* with log files

* lang?

* last resort

* wip

* test no det with general tests

* show tests live

* also include hidden integration tests

* without extra summary?

* revert

* last resort again

* tsquash on int64_t?

* tsquash on int64_t? mroe print

* writing to /tmp?

* all tests

* might be the fix?

* write to file

* fixed a few quiet mode no log file tests

* work on any branch for github tests, work on also release candidates for gitea tests

* added frame synchronizer tests to github workflow

* moved tests to run_tests.yaml from cmake.yaml

* documentation

* disabled general tests

---------

Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2026-02-03 11:45:12 +01:00
mazzol_a a390e580d2 Merge pull request #1375 from slsdetectorgroup/dev/xilinx_rm_powerdown
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xilinx server: remove powerdown for power regulators
2026-02-02 13:53:53 +01:00
mazzol_a aeed4762cf Merge branch 'developer' into dev/xilinx_rm_powerdown
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2026-02-02 12:17:07 +01:00
mazzol_a 809d70a950 Merge pull request #1376 from slsdetectorgroup/dev/mh1decode
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pyctbgui decoder for Matterhorn1 16 bits (1 and 4 counters)
2026-01-29 14:06:16 +01:00