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Author	SHA1	Message	Date
maliakal_d	da6620e0f5	binaries in	2026-05-01 11:50:49 +02:00
maliakal_d	b1a6f2ba32	missed a test marker	2026-05-01 11:25:51 +02:00
maliakal_d	1d20754ed8	xilinx: setup also done in stop server so that the clk is not 0	2026-04-30 17:13:34 +02:00
maliakal_d	ff8ea58dee	fixed m3 bug, binaries	2026-04-30 14:48:50 +02:00
maliakal_d	90aa409282	fixed xilinx freq conv as well	2026-04-30 11:55:24 +02:00
maliakal_d	259f9e9f90	periodleft and delayleft	2026-04-30 11:29:44 +02:00
maliakal_d	8dbe0a32a3	ctb is probably done	2026-04-30 11:15:31 +02:00
maliakal_d	96f7bc2685	some more changes to exptime and validations	2026-04-30 09:47:10 +02:00
maliakal_d	7b44caab98	missed in previous commit	2026-04-30 08:52:20 +02:00
maliakal_d	d616549f87	tolerance process	2026-04-29 16:42:54 +02:00
maliakal_d	c43959803e	get frequency only for that unit	2026-04-28 16:57:16 +02:00
maliakal_d	dc7ba60cc0	minor, default clk vals are 0 but set up at detector setup	2026-04-28 16:10:31 +02:00
maliakal_d	5360bf6d0f	minor, and binaries	2026-04-28 16:08:53 +02:00
maliakal_d	09922ddfb7	intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary	2026-04-28 16:01:36 +02:00
maliakal_d	d13585cbf4	removed Rep redundant in ToString for freq	2026-04-27 17:07:47 +02:00
maliakal_d	280e3254d1	minor: rounding test	2026-04-27 17:03:49 +02:00
maliakal_d	f6b67a8c0a	formatting	2026-04-27 17:00:02 +02:00
maliakal_d	b0f4aa1657	Merge branch 'developer' into dev/ctb_clocks	2026-04-27 16:58:44 +02:00
Martin Mueller	6bbbce5dc3	CTB: simplify power monitoring (#1428) ... * simplify power monitoring * removed register definitions not needed anymore, formatting * binaries updated --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>	2026-04-27 16:54:44 +02:00
muelle_m1	bd77ea231b	also added tolerance check for patwaittime	2026-04-24 15:07:49 +02:00
muelle_m1	795668be8a	insert tolerance check again	2026-04-24 13:42:13 +02:00
maliakal_d	8ff128b062	Dev/ctb clocks fix (#1434) ... * introduced new type Hz, typetraits, String conversions, command generation (not yet generated) * incorrect unit typo * cmd generation and compiles * default to MHz, removed space between units for consistency with timers, min and max checks for clks * in python, but need to change the default to Hz again for clean code and intuition * allow ints, doubles, implicit conversions * dont allow raw ints, doubles and implicit conversions * fixed tests * added operators for Hz in python * fix test for min clk for xilinx ctb * fix test * fix python tests * fixed xilinx period and default clks * test fix * removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb * removing 3 clock cycle code from xilinx as well * formatting * loadpattern before 3 clk cycles code * actualtime and measurement time to be implemented in 100ns already in fw * fix tests * pyzmq dependency forthe tests * fixed pyctbgui for freq	2026-04-23 17:27:13 +02:00
maliakal_d	49ef6df714	fix synchronizer test script (#1440)	2026-04-23 17:18:41 +02:00
maliakal_d	d1106fec41	Merge branch 'developer' into dev/ctb_clocks	2026-04-22 16:36:13 +02:00
mazzol_a	973bd89ca5	updated documentation workflow (#1436)	2026-04-21 11:56:19 +02:00
maliakal_d	c05d5a37cd	dev/ fix vchip and binaries (#1435) ... * updated binaries and fixed a warning by moving the usleep_bf to blackfin.c * suppressed warnings * cleaned up docs * renamed function --------- Co-authored-by: Alice <alice.mazzoleni@psi.ch>	2026-04-21 10:59:05 +02:00
Martin Mueller	326df1de97	fix pyctbgui powerindex (#1433) ... * fix pyctbgui powerindex * detangled power enable and power dac values * displaybox for vchip --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>	2026-04-17 09:25:40 +02:00
Martin Mueller	78edfe3b55	Running Matterhorn on altera CTB (#1427) ... * testing matterhorn1 SPI on altera CTB, works for dummy-chip * added bf_usleep with proper timing for blackfin * simplified spi firmware interface, removed write and readstrobe * define constant for BFIN spi sleep --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch>	2026-04-15 16:23:04 +02:00
maliakal_d	5ec5d46c48	Dev/ctb separate dac and power (#1420) ... * not allowing power names for dac names to prevent duplicate names * wip * v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power * binary in * dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands * wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested * wip. client and xilinx todo * wip: ctb power works, tests left * fixed some tests * added vchip check * python cmds still left. wip * fixed xilinx. python left * wip * wip. xilinx * fixed powerchip for ctb * power all returns all * configtransceiver is removed * wip python * wip * wip * wip * wip * wip * wip * wip xilinx * wip * wip * wip * pybindings * fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector * wip * fixed tests * fixes for python api * wip * python: moved powerlist to Ctb * fixed tests to work for powelist in Ctb * moved signallist, adclist, slowadc, slowadclist to Ctb * throw approperiate error when no modules added for powers * added dac test * fix dac default names and test for dacs * ctb dacs, yet to do othe rdacs * dacs should work now even in tests * run all tests * DetectorPowers->NamedPowers in ctb * comments * removed unnecessary test code * removed hard coded dac names in python NamedDacs and NamedPowers * minor * minor * fixed error messages * changed power to be able to set DAC directly, using enable and disable methods with enabled to get	2026-04-15 10:33:01 +02:00
muelle_m1	2372f93dd9	update help and comments	2026-03-19 15:23:50 +01:00
muelle_m1	614b5c56d9	change python and pyctbgui to accept and return floating point MHz	2026-03-19 15:10:03 +01:00
muelle_m1	6811bb1f33	added virtual check in Altera_PLL, update testcases	2026-03-19 11:49:47 +01:00
muelle_m1	0415911279	update default values in server defs	2026-03-19 11:30:40 +01:00
muelle_m1	27ea49c8e8	added tolerance to exptime, fixed test	2026-03-18 17:50:55 +01:00
muelle_m1	a810ddeaf4	do the same for dbit and adcclk	2026-03-18 15:50:18 +01:00
muelle_m1	339b96cdd3	changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?	2026-03-18 15:28:16 +01:00
muelle_m1	fc1f4b4a6a	change CTB and XCTB clock values to MHz, TODO: units and validation errors	2026-03-18 14:02:36 +01:00
muelle_m1	e2cb75c27d	Merge remote-tracking branch 'origin/developer' into dev/ctb_clocks	2026-03-18 10:05:51 +01:00
maliakal_d	4ee61ae791	ctb and xilinx: setting all dacs (normal, not power dacs) to 0 (not power down) at startup. This is safer than power down for 4 normal dacs. xilinx ctb: remove disable fmc at power off chip so one can power on and off the chip on their own (#1424)	2026-03-17 16:53:33 +01:00
muelle_m1	6b13336c95	add check for backwards compatibility	2026-03-12 15:31:30 +01:00
muelle_m1	778b497eb1	added time for firmware to measrue actual value after frequency change	2026-03-12 15:13:52 +01:00
muelle_m1	f9b3c4f9ce	round CTB clocks to next closest possible value, added freq measurement	2026-03-11 17:57:20 +01:00
mazzol_a	c86ca1eaec	per default pyqtgraph should read array as row-major (#1419) ... * per default pyqtgraph should read array as row-major * dont transform for analog images * never flip rows	2026-03-11 12:28:42 +01:00
maliakal_d	3846aec46e	Dev/jungfrau 1m root display support (#1364) ... * Aldo Mozzanica added support for 2 modules in 1M configuration for root display * deleted the wrong files	2026-03-05 17:13:38 +01:00
maliakal_d	6982b8cfa4	rm unnecessary hidden test tags (#1415) ... * removed hidden tags other than .detectorintegration and .disable_check_data_file * updated label, minor	2026-03-05 17:11:56 +01:00
maliakal_d	384b2480ab	Dev/fix no rx roi port (#1372) ... * rx_roi fixed when there is no roi for a particular port. Fixed tests for it * removing todo check if files created because its not enough to count matching pattern file names, but also look at timestamp and create files with timestamp else you read older ones. For now, checking individual rois is enough * restore md5 --------- Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>	2026-03-05 12:28:57 +01:00
Erik Fröjdh	a1b8dccdd9	added support for int() for RegisterAddress and RegisterValue (#1414)	2026-03-05 11:35:21 +01:00
Erik Fröjdh	9f72688b9c	Adding offset to RegisterAddress (#1413) ... * implemented + and += for RegisterAddres and tests plus test cleanup	2026-03-05 09:32:21 +01:00
mazzol_a	6e090dbba2	Dev/update workflows (#1406) ... * only run tests for pull-requests * build gui and simulators * trigger upon push to all branches * renamed workflows * added python tests * added colorama and numpy * added slsdet to pythonpath * updated workflow name	2026-03-02 14:30:27 +01:00
maliakal_d	60f5db1224	xilinx: slow adcs (#1405) ... * xilinx: slow adcs * minor * xilinx: max reference voltage back to 2500mV for slow adcs ad7689	2026-02-27 17:17:11 +01:00