11 Commits

Author	SHA1	Message	Date
Waldemar Koprek	f4c0185f31	Merge pull request #8 from paulscherrerinstitute/feature/se32 ... New features in branch feature/se32	2024-08-08 12:41:58 +02:00
Elmar Schmid	01de9bd1a9	Add register to control caching behavior on AXI link that performs the dma transfer	2024-08-08 11:53:32 +02:00
Elmar Schmid	16f13e64d7	Add internal data width as generic parameter	2024-08-08 11:49:45 +02:00
Elmar Schmid	3957ce32b5	Adapt interrupt generation logic to solve problem with missing interrupts.	2024-07-25 15:39:24 +02:00
KW82	a0f4eddf91	Updated instantiation of psi_common_async_fifo due to change of the port name	2024-01-26 10:48:07 +01:00
Elmar Schmid	12c010fe45	Add timeout control bits and logic to ignore timeout or configure framebased timeout in input logic.	2023-09-19 16:09:12 +02:00
stef_b	f6178e9dbd	Refactoring and compliant with 3.0.0 release psi_common	2023-04-14 17:36:50 +02:00
Oliver Bruendler	5390c0c3c0	BUGFIX: Workaround for ISE tools implementing memory as FFs in case of 1 stream	2019-11-25 10:23:36 +01:00
Oliver Bruendler	df29e19f6d	TIMING: Optimized timing on critical path between input FIFO and DMA ... Added pipeline stage after FIFO to reduce requirements of fall-through interface	2019-11-07 07:46:37 +01:00
Oliver Bruendler	7f22ec9050	BUGFIX: Made design working for 1 stream	2019-10-30 11:02:11 +01:00
Oliver Bruendler	d455112276	DEVEL: First open source release	2019-08-02 10:03:58 +02:00