AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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BUGFIX: Made design working for 1 stream

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This commit is contained in:
Oliver Bruendler
2019-10-30 11:02:11 +01:00
parent 3efc256530
commit 7f22ec9050
6 changed files with 682 additions and 18 deletions
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16
hdl/psi_ms_daq_daq_dma.vhd
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@ -68,15 +68,19 @@ architecture rtl of psi_ms_daq_daq_dma is
-- Constants
constant BufferFifoDepth_c : integer := 32;
-- Number of bits to encode stream is at least 1 (otherwise the special case for one stream would require separate code).
-- .. The overhead generated by this is regarded as aceptable (better wasting a few LUTs than much development time)
constant StreamBits_c : integer := max(log2ceil(Streams_g), 1);
-- Component Connection Signals
signal CmdFifo_Level_Dbg : std_logic_vector(log2ceil(Streams_g) downto 0);
signal CmdFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
signal CmdFifo_InData : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c-1 downto 0);
signal CmdFifo_OutData : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c-1 downto 0);
signal CmdFifo_Cmd : DaqSm2DaqDma_Cmd_t;
signal CmdFifo_Vld : std_logic;
signal RspFifo_Level_Dbg : std_logic_vector(log2ceil(Streams_g) downto 0);
signal RspFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
signal RspFifo_InData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
signal RspFifo_OutData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
signal DatFifo_Level_Dbg : std_logic_vector(log2ceil(BufferFifoDepth_c) downto 0);
@ -95,7 +99,7 @@ architecture rtl of psi_ms_daq_daq_dma is
RspFifo_Vld : std_logic;
RspFifo_Data : DaqDma2DaqSm_Resp_t;
Mem_DataVld : std_logic;
StreamStdlv : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
StreamStdlv : std_logic_vector(StreamBits_c-1 downto 0);
RemWen : std_logic;
RemWrBytes : std_logic_vector(2 downto 0);
RemData : std_logic_vector(63 downto 0);
@ -300,7 +304,7 @@ begin
i_fifocmd : entity work.psi_common_sync_fifo
generic map (
Width_g => DaqSm2DaqDma_Cmd_Size_c,
Depth_g => Streams_g,
Depth_g => 2**StreamBits_c,
RamStyle_g => "distributed",
RamBehavior_g => "RBW"
)
@ -322,7 +326,7 @@ begin
i_fiforsp : entity work.psi_common_sync_fifo
generic map (
Width_g => DaqDma2DaqSm_Resp_Size_c,
Depth_g => Streams_g,
Depth_g => 2**StreamBits_c,
RamStyle_g => "distributed",
RamBehavior_g => "RBW"
)
@ -366,7 +370,7 @@ begin
-- *** Remaining Data RAM ***
i_remram : entity work.psi_common_sdp_ram
generic map (
Depth_g => Streams_g,
Depth_g => 2**StreamBits_c,
Width_g => 1+1+3+64,
IsAsync_g => false,
RamStyle_g => "distributed",

26
hdl/psi_ms_daq_daq_sm.vhd
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@ -76,6 +76,10 @@ end entity;
------------------------------------------------------------------------------
architecture rtl of psi_ms_daq_daq_sm is
-- Number of bits to encode stream is at least 1 (otherwise the special case for one stream would require separate code).
-- .. The overhead generated by this is regarded as aceptable (better wasting a few LUTs than much development time)
constant StreamBits_c : integer := max(log2ceil(Streams_g), 1);
-- Function Definitions
function GetBitsOfStreamPrio( InputVector : std_logic_vector;
Prio : integer)
@ -132,10 +136,10 @@ architecture rtl of psi_ms_daq_daq_sm is
signal IrqFifoAlmFull : std_logic;
signal IrqFifoEmpty : std_logic;
signal IrqFifoGenIrq : std_logic;
signal IrqFifoStream : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
signal IrqFifoStream : std_logic_vector(StreamBits_c-1 downto 0);
signal IrqLastWinNr : std_logic_vector(log2ceil(Windows_g)-1 downto 0);
signal IrqFifoIn : std_logic_vector(log2ceil(Streams_g)+log2ceil(Windows_g) downto 0);
signal IrqFifoOut : std_logic_vector(log2ceil(Streams_g)+log2ceil(Windows_g) downto 0);
signal IrqFifoIn : std_logic_vector(StreamBits_c+log2ceil(Windows_g) downto 0);
signal IrqFifoOut : std_logic_vector(StreamBits_c+log2ceil(Windows_g) downto 0);
-- Types
type State_t is (Idle_s, CheckPrio1_s, CheckPrio2_s, CheckPrio3_s, CheckResp_s, TlastCheck_s, ReadCtxStr_s, First_s, ReadCtxWin_s, CalcAccess0_s, CalcAccess1_s, ProcResp0_s, NextWin_s, WriteCtx_s);
@ -178,7 +182,7 @@ architecture rtl of psi_ms_daq_daq_sm is
HndlWinBytes : std_logic_vector(32 downto 0);
HndlWinLast : std_logic_vector(31 downto 0);
HndlTs : std_logic_vector(63 downto 0);
TfDoneCnt : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
TfDoneCnt : std_logic_vector(StreamBits_c-1 downto 0);
TfDoneReg : std_logic;
HndlWinDone : std_logic;
CtxStr_Cmd : ToCtxStr_t;
@ -681,15 +685,15 @@ begin
-- *** IRQ Information FIFO ***
-- input assembly
IrqFifoIn(log2ceil(Streams_g)-1 downto 0) <= std_logic_vector(to_unsigned(r.HndlStream, log2ceil(Streams_g)));
IrqFifoIn(log2ceil(Streams_g)+log2ceil(Windows_g)-1 downto log2ceil(Streams_g)) <= r.HndlLastWinNr;
IrqFifoIn(IrqFifoIn'high) <= r.HndlWinDone;
IrqFifoIn(StreamBits_c-1 downto 0) <= std_logic_vector(to_unsigned(r.HndlStream, StreamBits_c));
IrqFifoIn(StreamBits_c+log2ceil(Windows_g)-1 downto StreamBits_c) <= r.HndlLastWinNr;
IrqFifoIn(IrqFifoIn'high) <= r.HndlWinDone;
-- Instantiation
i_irq_fifo : entity work.psi_common_sync_fifo
generic map (
Width_g => log2ceil(Streams_g)+log2ceil(Windows_g)+1,
Depth_g => Streams_g*4,
Width_g => StreamBits_c+log2ceil(Windows_g)+1,
Depth_g => 2**StreamBits_c*4,
AlmFullOn_g => true,
AlmFullLevel_g => Streams_g*3,
RamStyle_g => "distributed"
@ -706,8 +710,8 @@ begin
);
-- Output disassembly
IrqFifoStream <= IrqFifoOut(log2ceil(Streams_g)-1 downto 0);
IrqLastWinNr <= IrqFifoOut(log2ceil(Streams_g)+log2ceil(Windows_g)-1 downto log2ceil(Streams_g));
IrqFifoStream <= IrqFifoOut(StreamBits_c-1 downto 0);
IrqLastWinNr <= IrqFifoOut(StreamBits_c+log2ceil(Windows_g)-1 downto StreamBits_c);
IrqFifoGenIrq <= IrqFifoOut(IrqFifoOut'high);

2
hdl/psi_ms_daq_reg_axi.vhd
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@ -206,7 +206,7 @@ begin
v.Reg_Mode_Arm := (others => '0');
v.MaxLvlClr := (others => '0');
if AccAddr(15 downto 9) = X"0" & "001" then
Stream_v := to_integer(unsigned(AccAddr(8 downto 4)));
Stream_v := work.psi_common_math_pkg.min(to_integer(unsigned(AccAddr(8 downto 4))), Streams_g-1);
-- MAXLVLn
if AccAddr(3 downto 0) = X"0" then