AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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Merge pull request #8 from paulscherrerinstitute/feature/se32

Browse Source 
New features in branch feature/se32
This commit is contained in:
Waldemar Koprek
2024-08-08 12:41:58 +02:00
committed by GitHub
parent 0dfa3ef76b 01de9bd1a9
commit f4c0185f31
20 changed files with 161 additions and 81 deletions
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45
hdl/psi_ms_daq_axi.vhd
View File

@ -31,6 +31,7 @@ entity psi_ms_daq_axi is
StreamTsFifoDepth_g : t_ainteger := (16, 16);
StreamUseTs_g : t_abool := (true, true);
-- Recording
IntDataWidth_g : positive := 64;
MaxWindows_g : positive range 1 to 32 := 16;
MinBurstSize_g : integer range 1 to 512 := 512;
MaxBurstSize_g : integer range 1 to 512 := 512;
@ -159,14 +160,14 @@ architecture rtl of psi_ms_daq_axi is
-- Input/Dma
signal InpDma_Vld : std_logic_vector(Streams_g - 1 downto 0);
signal InpDma_Rdy : std_logic_vector(Streams_g - 1 downto 0);
signal InpDma_Data : Input2Daq_Data_a(Streams_g - 1 downto 0);
signal InpDma_Data : Input2Daq_Data_a(Streams_g - 1 downto 0)(Data(IntDataWidth_g-1 downto 0), Bytes(log2ceil(IntDataWidth_g/8) downto 0));
-- Dma/Mem
signal DmaMem_CmdAddr : std_logic_vector(31 downto 0);
signal DmaMem_CmdSize : std_logic_vector(31 downto 0);
signal DmaMem_CmdVld : std_logic;
signal DmaMem_CmdRdy : std_logic;
signal DmaMem_DatData : std_logic_vector(63 downto 0);
signal DmaMem_DatData : std_logic_vector(IntDataWidth_g-1 downto 0);
signal DmaMem_DatVld : std_logic;
signal DmaMem_DatRdy : std_logic;
@ -181,6 +182,10 @@ architecture rtl of psi_ms_daq_axi is
signal Cfg_RecMode : t_aslv2(Streams_g - 1 downto 0);
signal Cfg_ToDisable : std_logic_vector(Streams_g -1 downto 0);
signal Cfg_FrameTo : std_logic_vector(Streams_g -1 downto 0);
signal AWCache : t_aslv4(2 downto 0) := (others => (others => '0'));
signal AWProt : t_aslv3(2 downto 0) := (others => (others => '0'));
signal ARCache : t_aslv4(2 downto 0) := (others => (others => '0'));
signal ARProt : t_aslv3(2 downto 0) := (others => (others => '0'));
-- Status
signal Stat_StrIrq : std_logic_vector(Streams_g - 1 downto 0);
signal Stat_StrLastWin : WinType_a(Streams_g - 1 downto 0);
@ -203,6 +208,23 @@ begin
M_Axi_Areset <= not M_Axi_Aresetn;
S_Axi_Areset <= not S_Axi_Aresetn;
-- Sync quasi static vecctors
sync_apc_reg : process(M_Axi_Aclk)
begin
if rising_edge(M_Axi_Aclk) then
for i in 1 to 2 loop
AWProt(i) <= AWProt(i-1);
AWCache(i) <= AWCache(i-1);
ARProt(i) <= ARProt(i-1);
ARCache(i) <= ARCache(i-1);
end loop;
end if;
end process;
M_Axi_AwCache <= AWCache(2);
M_Axi_AwProt <= AWProt(2);
M_Axi_ArCache <= ARCache(2);
M_Axi_ArProt <= ARProt(2);
--------------------------------------------
-- Register Interface
--------------------------------------------
@ -251,6 +273,10 @@ begin
S_Axi_BValid => S_Axi_BValid,
S_Axi_BReady => S_Axi_BReady,
IrqOut => Irq,
AWCache => AWCache(0),
AWProt => AWProt(0),
ARCache => ARCache(0),
ARProt => ARProt(0),
PostTrig => Cfg_PostTrig,
Arm => Cfg_Arm,
IsArmed => Stat_IsArmed,
@ -290,7 +316,8 @@ begin
StreamTimeout_g => StreamTimeout_c(str),
StreamClkFreq_g => StreamClkFreq_c(str),
StreamTsFifoDepth_g => StreamTsFifoDepth_c(str),
StreamUseTs_g => StreamUseTs_c(str)
StreamUseTs_g => StreamUseTs_c(str),
IntDataWidth_g => IntDataWidth_g
)
port map(
Str_Clk => Str_Clk(str),
@ -367,7 +394,8 @@ begin
--------------------------------------------
i_dma : entity work.psi_ms_daq_daq_dma
generic map(
Streams_g => Streams_g
Streams_g => Streams_g,
IntDataWidth_g => IntDataWidth_g
)
port map(
Clk => M_Axi_Aclk,
@ -395,6 +423,7 @@ begin
--------------------------------------------
i_memif : entity work.psi_ms_daq_axi_if
generic map(
IntDataWidth_g => IntDataWidth_g,
AxiDataWidth_g => AxiDataWidth_g,
AxiMaxBeats_g => AxiMaxBurstBeats_g,
AxiMaxOpenTrasactions_g => AxiMaxOpenTrasactions_g,
@ -419,8 +448,8 @@ begin
M_Axi_AwSize => M_Axi_AwSize,
M_Axi_AwBurst => M_Axi_AwBurst,
M_Axi_AwLock => M_Axi_AwLock,
M_Axi_AwCache => M_Axi_AwCache,
M_Axi_AwProt => M_Axi_AwProt,
M_Axi_AwCache => open, --M_Axi_AwCache
M_Axi_AwProt => open, --M_Axi_AwProt
M_Axi_AwValid => M_Axi_AwValid,
M_Axi_AwReady => M_Axi_AwReady,
M_Axi_WData => M_Axi_WData,
@ -436,8 +465,8 @@ begin
M_Axi_ArSize => M_Axi_ArSize,
M_Axi_ArBurst => M_Axi_ArBurst,
M_Axi_ArLock => M_Axi_ArLock,
M_Axi_ArCache => M_Axi_ArCache,
M_Axi_ArProt => M_Axi_ArProt,
M_Axi_ArCache => open, --M_Axi_ArCache
M_Axi_ArProt => open, --M_Axi_ArProt
M_Axi_ArValid => M_Axi_ArValid,
M_Axi_ArReady => M_Axi_ArReady,
M_Axi_RData => M_Axi_RData,

6
hdl/psi_ms_daq_axi_if.vhd
View File

@ -19,6 +19,7 @@ use work.psi_common_math_pkg.all;
------------------------------------------------------------------------------
entity psi_ms_daq_axi_if is
generic(
IntDataWidth_g : positive := 64;
AxiDataWidth_g : natural range 64 to 1024 := 64;
AxiMaxBeats_g : natural range 1 to 256 := 256;
AxiMaxOpenTrasactions_g : natural range 1 to 8 := 8;
@ -37,7 +38,7 @@ entity psi_ms_daq_axi_if is
Cmd_Vld : in std_logic;
Cmd_Rdy : out std_logic;
-- Write Data
Dat_Data : in std_logic_vector(63 downto 0);
Dat_Data : in std_logic_vector(IntDataWidth_g - 1 downto 0);
Dat_Vld : in std_logic;
Dat_Rdy : out std_logic;
-- Response
@ -133,7 +134,7 @@ begin
axi_max_open_trasactions_g => AxiMaxOpenTrasactions_g,
user_transaction_size_bits_g => 32,
data_fifo_depth_g => DataFifoDepth_g,
data_width_g => 64,
data_width_g => IntDataWidth_g,
impl_read_g => false,
impl_write_g => true,
ram_behavior_g => RamBehavior_g
@ -208,4 +209,3 @@ begin
Done <= DoneI or ErrorI;
end;

62
hdl/psi_ms_daq_daq_dma.vhd
View File

@ -30,7 +30,8 @@ use work.psi_ms_daq_pkg.all;
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg,work.psi_tb_activity_pkg $$
entity psi_ms_daq_daq_dma is
generic(
Streams_g : positive range 1 to 32 := 4 -- $$ constant=4 $$
Streams_g : positive range 1 to 32 := 4; -- $$ constant=4 $$
IntDataWidth_g : positive := 64 -- $$ constant=64 $$
);
port(
-- Control signals
@ -48,14 +49,14 @@ entity psi_ms_daq_daq_dma is
-- Input handling connections
Inp_Vld : in std_logic_vector(Streams_g - 1 downto 0); -- $$ proc=input $$
Inp_Rdy : out std_logic_vector(Streams_g - 1 downto 0); -- $$ proc=input $$
Inp_Data : in Input2Daq_Data_a(Streams_g - 1 downto 0); -- $$ proc=input $$
Inp_Data : in Input2Daq_Data_a(Streams_g - 1 downto 0)(Data(IntDataWidth_g-1 downto 0), Bytes(log2ceil(IntDataWidth_g/8) downto 0)); -- $$ proc=input $$
-- Memory interface connections
Mem_CmdAddr : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
Mem_CmdSize : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
Mem_CmdVld : out std_logic; -- $$ proc=mem_cmd $$
Mem_CmdRdy : in std_logic; -- $$ proc=mem_cmd $$
Mem_DatData : out std_logic_vector(63 downto 0); -- $$ proc=mem_dat $$
Mem_DatData : out std_logic_vector(IntDataWidth_g-1 downto 0); -- $$ proc=mem_dat $$
Mem_DatVld : out std_logic; -- $$ proc=mem_dat $$
Mem_DatRdy : in std_logic -- $$ proc=mem_dat $$
);
@ -72,6 +73,8 @@ architecture rtl of psi_ms_daq_daq_dma is
-- Number of bits to encode stream is at least 1 (otherwise the special case for one stream would require separate code).
-- .. The overhead generated by this is regarded as aceptable (better wasting a few LUTs than much development time)
constant StreamBits_c : integer := max(log2ceil(Streams_g), 1);
constant IntDataBytes_c : positive := IntDataWidth_g/8;
constant BytesWidth_c : positive := log2ceil(IntDataBytes_c);
-- Component Connection Signals
signal CmdFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
@ -84,10 +87,12 @@ architecture rtl of psi_ms_daq_daq_dma is
signal RspFifo_OutData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c - 1 downto 0);
signal DatFifo_Level_Dbg : std_logic_vector(log2ceil(BufferFifoDepth_c) downto 0);
signal DatFifo_AlmFull : std_logic;
signal Rem_RdBytes : std_logic_vector(2 downto 0);
signal Rem_Data : std_logic_vector(63 downto 0);
signal Rem_RdBytes : std_logic_vector(BytesWidth_c - 1 downto 0);
signal Rem_Data : std_logic_vector(IntDataWidth_g - 1 downto 0);
signal Rem_Trigger : std_logic;
signal Rem_Last : std_logic;
signal Rem_Data_Fifo_In : std_logic_vector(BytesWidth_c + IntDataWidth_g + 1 downto 0);
signal Rem_Data_Fifo_Out : std_logic_vector(BytesWidth_c + IntDataWidth_g + 1 downto 0);
-- Types
type State_t is (Idle_s, RemRd1_s, RemRd2_s, Transfer_s, Done_s, Cmd_s);
@ -100,8 +105,8 @@ architecture rtl of psi_ms_daq_daq_dma is
Mem_DataVld : std_logic;
StreamStdlv : std_logic_vector(StreamBits_c - 1 downto 0);
RemWen : std_logic;
RemWrBytes : std_logic_vector(2 downto 0);
RemData : std_logic_vector(63 downto 0);
RemWrBytes : std_logic_vector(BytesWidth_c - 1 downto 0);
RemData : std_logic_vector(IntDataWidth_g - 1 downto 0);
RemTrigger : std_logic;
RemLast : std_logic;
RemWrTrigger : std_logic;
@ -113,12 +118,12 @@ architecture rtl of psi_ms_daq_daq_dma is
HndlStream : integer range 0 to MaxStreams_c - 1;
HndlAddress : std_logic_vector(31 downto 0);
UpdateLast : std_logic;
HndlSft : unsigned(2 downto 0);
HndlSft : unsigned(BytesWidth_c-1 downto 0);
FirstDma : std_logic_vector(Streams_g - 1 downto 0);
Mem_CmdVld : std_logic;
Trigger : std_logic;
Last : std_logic;
DataSft : std_logic_vector(127 downto 0);
DataSft : std_logic_vector(2*IntDataWidth_g - 1 downto 0);
NextDone : std_logic;
DataWritten : std_logic;
HasLast : std_logic_vector(Streams_g - 1 downto 0);
@ -174,7 +179,7 @@ begin
v.RemLast := '0';
else
v.HndlSft := unsigned(Rem_RdBytes);
v.DataSft(127 downto 64) := Rem_Data;
v.DataSft(2*IntDataWidth_g - 1 downto IntDataWidth_g) := Rem_Data;
v.RdBytes := resize(unsigned(Rem_RdBytes), v.RdBytes'length);
v.RemTrigger := Rem_Trigger;
v.RemLast := Rem_Last;
@ -192,7 +197,7 @@ begin
if r.NextDone = '0' and Inp_Vld(r.HndlStream) = '1' and r.RemLast = '0' then
v.RdBytes := r.RdBytes + unsigned(Inp_Data(r.HndlStream).Bytes);
end if;
v.WrBytes := r.WrBytes + 8;
v.WrBytes := r.WrBytes + IntDataBytes_c;
-- Combinatorial handling because of fall-through interface at input
if r.RdBytes < r.HndlMaxSize and r.NextDone = '0' and r.RemLast = '0' then
Inp_Rdy(r.HndlStream) <= '1';
@ -200,7 +205,7 @@ begin
-- Handling of last frame
if (Inp_Data(r.HndlStream).Last = '1') or (r.RemLast = '1') then
-- Do one more word if not all data can be transferred in the current beat (NextDone = 1)
if (r.HndlSft + unsigned(Inp_Data(r.HndlStream).Bytes) <= 8) or (r.RemLast = '1') then
if (r.HndlSft + unsigned(Inp_Data(r.HndlStream).Bytes) <= IntDataBytes_c) or (r.RemLast = '1') then
v.State := Done_s;
else
v.NextDone := '1';
@ -214,8 +219,8 @@ begin
v.State := Done_s;
end if;
-- Data handling
v.DataSft(63 downto 0) := r.DataSft(127 downto 64);
v.DataSft(8 * to_integer(r.HndlSft) + 63 downto 8 * to_integer(r.HndlSft)) := Inp_Data(r.HndlStream).Data;
v.DataSft(IntDataWidth_g - 1 downto 0) := r.DataSft(2*IntDataWidth_g - 1 downto IntDataWidth_g);
v.DataSft(8 * to_integer(r.HndlSft) + IntDataWidth_g - 1 downto 8 * to_integer(r.HndlSft)) := Inp_Data(r.HndlStream).Data;
if Inp_Vld(r.HndlStream) = '1' or r.HndlSft /= 0 then
v.Mem_DataVld := '1';
v.DataWritten := '1';
@ -236,7 +241,7 @@ begin
v.RemWrBytes := (others => '0');
v.HasLast(r.HndlStream) := '0';
end if;
v.RemData := v.DataSft(8 * RemSft_v + 63 downto 8 * RemSft_v);
v.RemData := v.DataSft(8 * RemSft_v + IntDataWidth_g - 1 downto 8 * RemSft_v);
v.State := Cmd_s;
if r.DataWritten = '1' then
v.Mem_CmdVld := '1';
@ -344,7 +349,7 @@ begin
-- Rdy is not required since the data pipeline is stopped based on the almost full flag
i_fifodata : entity work.psi_common_sync_fifo
generic map(
width_g => 64,
width_g => IntDataWidth_g,
depth_g => BufferFifoDepth_c,
alm_full_on_g => true,
alm_full_level_g => BufferFifoDepth_c / 2,
@ -354,7 +359,7 @@ begin
port map(
clk_i => Clk,
rst_i => Rst,
dat_i => r.DataSft(63 downto 0),
dat_i => r.DataSft(IntDataWidth_g-1 downto 0),
vld_i => r.Mem_DataVld,
dat_o => Mem_DatData,
vld_o => Mem_DatVld,
@ -364,10 +369,15 @@ begin
);
-- *** Remaining Data RAM ***
Rem_Data_Fifo_In(BytesWidth_c + IntDataWidth_g + 1) <= r.RemWrLast;
Rem_Data_Fifo_In(BytesWidth_c + IntDataWidth_g) <= r.RemWrTrigger;
Rem_Data_Fifo_In(BytesWidth_c + IntDataWidth_g - 1 downto IntDataWidth_g) <= r.RemWrBytes;
Rem_Data_Fifo_In(IntDataWidth_g - 1 downto 0) <= r.RemData;
i_remram : entity work.psi_common_sdp_ram
generic map(
depth_g => 2**StreamBits_c,
width_g => 1 + 1 + 3 + 64,
width_g => 1 + 1 + BytesWidth_c + IntDataWidth_g,
is_async_g => false,
ram_style_g => "distributed",
ram_behavior_g => "RBW"
@ -377,16 +387,14 @@ begin
rd_clk_i => Rst,
wr_addr_i => r.StreamStdlv,
wr_i => r.RemWen,
wr_dat_i(68) => r.RemWrLast,
wr_dat_i(67) => r.RemWrTrigger,
wr_dat_i(66 downto 64) => r.RemWrBytes,
wr_dat_i(63 downto 0) => r.RemData,
wr_dat_i => Rem_Data_Fifo_In,
rd_addr_i => r.StreamStdlv,
rd_dat_o(68) => Rem_Last,
rd_dat_o(67) => Rem_Trigger,
rd_dat_o(66 downto 64) => Rem_RdBytes,
rd_dat_o(63 downto 0) => Rem_Data
rd_dat_o => Rem_Data_Fifo_Out
);
end;
Rem_Last <= Rem_Data_Fifo_Out(BytesWidth_c + IntDataWidth_g + 1);
Rem_Trigger <= Rem_Data_Fifo_Out(BytesWidth_c + IntDataWidth_g);
Rem_RdBytes <= Rem_Data_Fifo_Out(BytesWidth_c + IntDataWidth_g - 1 downto IntDataWidth_g);
Rem_Data <= Rem_Data_Fifo_Out(IntDataWidth_g - 1 downto 0);
end;

43
hdl/psi_ms_daq_input.vhd
View File

@ -33,7 +33,8 @@ entity psi_ms_daq_input is
StreamTimeout_g : real := 1.0e-3; -- Timeout in seconds $$ constant=10.0e-6 $$
StreamClkFreq_g : real := 125.0e6; -- Input clock frequency in Hz $$ constant=125.0e6 $$
StreamTsFifoDepth_g : positive := 16; -- Timestamp FIFO depth $$ constant=3 $$
StreamUseTs_g : boolean := true -- Enable/Disable the timestamp acquisition $$ constant=true $$
StreamUseTs_g : boolean := true; -- Enable/Disable the timestamp acquisition $$ constant=true $$
IntDataWidth_g : positive := 64
);
port(
-- Data Stream Input
@ -62,7 +63,7 @@ entity psi_ms_daq_input is
-- DAQ logic Connections
Daq_Vld : out std_logic; -- $$ proc=daq $$
Daq_Rdy : in std_logic; -- $$ proc=daq $$
Daq_Data : out Input2Daq_Data_t; -- $$ proc=daq $$
Daq_Data : out Input2Daq_Data_t(Data(IntDataWidth_g-1 downto 0), Bytes(log2ceil(IntDataWidth_g/8) downto 0)); -- $$ proc=daq $$
Daq_Level : out std_logic_vector(15 downto 0); -- $$ proc=daq $$
Daq_HasLast : out std_logic; -- $$ proc=daq $$
@ -83,16 +84,18 @@ architecture rtl of psi_ms_daq_input is
-- Constants
constant TimeoutLimit_c : integer := integer(StreamClkFreq_g * StreamTimeout_g) - 1;
constant WconvFactor_c : positive := 64 / StreamWidth_g;
constant WconvFactor_c : positive := IntDataWidth_g / StreamWidth_g;
constant BytesWidth_c : positive := log2ceil(IntDataWidth_g/8) + 1;
constant TlastCntWidth_c : positive := log2ceil(StreamBuffer_g) + 1;
constant DataFifoWidth_c : positive := IntDataWidth_g + BytesWidth_c + 2;
-- Two process method
type two_process_r is record
ModeReg : RecMode_t;
ArmReg : std_logic;
DataSftReg : std_logic_vector(63 downto 0);
DataSftReg : std_logic_vector(IntDataWidth_g-1 downto 0);
WordCnt : unsigned(log2ceil(WconvFactor_c) downto 0);
DataFifoBytes : unsigned(3 downto 0);
DataFifoBytes : unsigned(BytesWidth_c-1 downto 0);
TrigLatch : std_logic;
DataFifoVld : std_logic;
DataFifoIsTo : std_logic;
@ -115,16 +118,16 @@ architecture rtl of psi_ms_daq_input is
-- Data FIFO signals
signal DataFifo_InRdy : std_logic;
signal DataFifo_InData : std_logic_vector(69 downto 0);
signal DataFifo_OutData : std_logic_vector(69 downto 0);
signal DataFifo_PlData : std_logic_vector(69 downto 0);
signal DataFifo_InData : std_logic_vector(DataFifoWidth_c-1 downto 0);
signal DataFifo_OutData : std_logic_vector(DataFifoWidth_c-1 downto 0);
signal DataFifo_PlData : std_logic_vector(DataFifoWidth_c-1 downto 0);
signal DataFifo_PlVld : std_logic;
signal DataFifo_PlRdy : std_logic;
signal DataFifo_Level : std_logic_vector(log2ceil(StreamBuffer_g) downto 0);
signal DataPl_Level : unsigned(1 downto 0);
-- Internally reused signals
signal Daq_Data_I : Input2Daq_Data_t;
signal Daq_Data_I : Input2Daq_Data_t(Data(IntDataWidth_g-1 downto 0), Bytes(BytesWidth_c-1 downto 0));
signal Daq_Vld_I : std_logic;
signal Daq_HasLast_I : std_logic;
signal Ts_Vld_I : std_logic;
@ -273,7 +276,7 @@ begin
-- Process input data
if ProcessSample_v and r.RecEna = '1' then
v.WordCnt := r.WordCnt + 1;
-- Write because 64-bits are ready
-- Write because full word is ready
if r.WordCnt = WconvFactor_c - 1 then
v.DataFifoVld := r.DataFifoVld or r.RecEna;
end if;
@ -486,14 +489,14 @@ begin
);
-- Data FIFO
DataFifo_InData(63 downto 0) <= r.DataSftReg;
DataFifo_InData(67 downto 64) <= std_logic_vector(r.DataFifoBytes);
DataFifo_InData(68) <= r.DataFifoIsTo;
DataFifo_InData(69) <= r.DataFifoIsTrig;
DataFifo_InData(IntDataWidth_g-1 downto 0) <= r.DataSftReg;
DataFifo_InData(IntDataWidth_g+BytesWidth_c-1 downto IntDataWidth_g) <= std_logic_vector(r.DataFifoBytes);
DataFifo_InData(DataFifo_InData'high - 1) <= r.DataFifoIsTo;
DataFifo_InData(DataFifo_InData'high) <= r.DataFifoIsTrig;
i_dfifo : entity work.psi_common_async_fifo
generic map(
width_g => 70,
width_g => DataFifoWidth_c,
depth_g => StreamBuffer_g,
afull_on_g => false,
aempty_on_g => false
@ -515,7 +518,7 @@ begin
-- An additional pipeline stage after the FIFO is required for timing reasons
i_dplstage : entity work.psi_common_pl_stage
generic map(
width_g => 70,
width_g => DataFifoWidth_c,
use_rdy_g => true
)
port map(
@ -530,10 +533,10 @@ begin
);
Str_Rdy <= DataFifo_InRdy;
Daq_Data_I.Data <= DataFifo_OutData(63 downto 0);
Daq_Data_I.Bytes <= DataFifo_OutData(67 downto 64);
Daq_Data_I.IsTo <= DataFifo_OutData(68);
Daq_Data_I.IsTrig <= DataFifo_OutData(69);
Daq_Data_I.Data <= DataFifo_OutData(IntDataWidth_g-1 downto 0);
Daq_Data_I.Bytes <= DataFifo_OutData(IntDataWidth_g+BytesWidth_c-1 downto IntDataWidth_g);
Daq_Data_I.IsTo <= DataFifo_OutData(DataFifo_OutData'high-1);
Daq_Data_I.IsTrig <= DataFifo_OutData(DataFifo_OutData'high);
Daq_Data_I.Last <= Daq_Data_I.IsTo or Daq_Data_I.IsTrig;
Daq_Data <= Daq_Data_I;
Daq_Vld <= Daq_Vld_I;

4
hdl/psi_ms_daq_pkg.vhd
View File

@ -36,8 +36,8 @@ package psi_ms_daq_pkg is
type Input2Daq_Data_t is record
Last : std_logic;
Data : std_logic_vector(63 downto 0);
Bytes : std_logic_vector(3 downto 0);
Data : std_logic_vector;
Bytes : std_logic_vector;
IsTo : std_logic;
IsTrig : std_logic;
end record;

28
hdl/psi_ms_daq_reg_axi.vhd
View File

@ -79,6 +79,10 @@ entity psi_ms_daq_reg_axi is
ToDisable : out std_logic_vector(Streams_g - 1 downto 0);
FrameTo : out std_logic_vector(Streams_g - 1 downto 0);
IrqOut : out std_logic;
AWCache : out std_logic_vector(3 downto 0);
AWProt : out std_logic_vector(2 downto 0);
ARCache : out std_logic_vector(3 downto 0);
ARProt : out std_logic_vector(2 downto 0);
-- Memory Interfae Clock domain control singals
ClkMem : in std_logic;
RstMem : in std_logic;
@ -104,6 +108,10 @@ architecture rtl of psi_ms_daq_reg_axi is
Reg_IrqVec : std_logic_vector(Streams_g - 1 downto 0);
Reg_IrqEna : std_logic_vector(Streams_g - 1 downto 0);
Reg_StrEna : std_logic_vector(Streams_g - 1 downto 0);
Reg_AcpCfg_ARProt : std_logic_vector(2 downto 0);
Reg_AcpCfg_ARCache : std_logic_vector(3 downto 0);
Reg_AcpCfg_AWProt : std_logic_vector(2 downto 0);
Reg_AcpCfg_AWCache : std_logic_vector(3 downto 0);
Reg_PostTrig : t_aslv32(Streams_g - 1 downto 0);
Reg_Mode_Recm : t_aslv2(Streams_g - 1 downto 0);
Reg_Mode_Arm : std_logic_vector(Streams_g - 1 downto 0);
@ -201,6 +209,18 @@ begin
end if;
RegRdVal(16#20# / 4)(Streams_g - 1 downto 0) <= r.Reg_StrEna;
-- STRENA
if RegWr(16#24# / 4) = '1' then
v.Reg_AcpCfg_ARProt := RegWrVal(16#24# / 4)( 2 downto 0);
v.Reg_AcpCfg_ARCache := RegWrVal(16#24# / 4)( 7 downto 4);
v.Reg_AcpCfg_AWProt := RegWrVal(16#24# / 4)(10 downto 8);
v.Reg_AcpCfg_AWCache := RegWrVal(16#24# / 4)(15 downto 12);
end if;
RegRdVal(16#24# / 4)( 2 downto 0) <= r.Reg_AcpCfg_ARProt;
RegRdVal(16#24# / 4)( 7 downto 4) <= r.Reg_AcpCfg_ARCache;
RegRdVal(16#24# / 4)(10 downto 8) <= r.Reg_AcpCfg_AWProt;
RegRdVal(16#24# / 4)(15 downto 12) <= r.Reg_AcpCfg_AWCache;
-- *** Stream Register Accesses ***
v.RegRdval := (others => '0');
v.Reg_Mode_Arm := (others => '0');
@ -296,6 +316,10 @@ begin
RecMode <= r.Reg_Mode_Recm;
ToDisable <= r.Reg_Mode_ToDisable;
FrameTo <= r.Reg_Mode_FrameTo;
ARProt <= r.Reg_AcpCfg_ARProt;
ARCache <= r.Reg_AcpCfg_ARCache;
AWProt <= r.Reg_AcpCfg_AWProt;
AWCache <= r.Reg_AcpCfg_AWCache;
--------------------------------------------
-- Sequential Process
@ -310,6 +334,10 @@ begin
r.Reg_IrqVec <= (others => '0');
r.Reg_IrqEna <= (others => '0');
r.Reg_StrEna <= (others => '0');
r.Reg_AcpCfg_ARProt <= (others => '0');
r.Reg_AcpCfg_ARCache <= (others => '0');
r.Reg_AcpCfg_AWProt <= (others => '0');
r.Reg_AcpCfg_AWCache <= (others => '0');
r.Irq <= '0';
r.Reg_PostTrig <= (others => (others => '0'));
r.Reg_Mode_Recm <= (others => (others => '0'));