AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Adapt interrupt generation logic to solve problem with missing interrupts.

Browse Source
This commit is contained in:
schmid_e
2024-07-25 15:39:24 +02:00
parent a0f4eddf91
commit 3957ce32b5
1 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
hdl/psi_ms_daq_daq_sm.vhd
View File

@ -576,11 +576,12 @@ begin
if (unsigned(r.TfDoneCnt) /= 0) and (IrqFifoEmpty = '0') then
v.IrqFifoRead := '1';
v.TfDoneCnt := std_logic_vector(unsigned(v.TfDoneCnt) - 1);
-- Generate IRQ if required
if IrqFifoGenIrq = '1' then
v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1';
v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5));
end if;
end if;
-- Generate IRQ if required
if IrqFifoGenIrq = '1' and r.IrqFifoRead = '1' then
v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1';
v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5));
end if;
-- *** Assign to signal ***