From 3957ce32b50c08610136fef2e4a86d56990defad Mon Sep 17 00:00:00 2001 From: Elmar Schmid Date: Thu, 25 Jul 2024 15:39:24 +0200 Subject: [PATCH] Adapt interrupt generation logic to solve problem with missing interrupts. --- hdl/psi_ms_daq_daq_sm.vhd | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hdl/psi_ms_daq_daq_sm.vhd b/hdl/psi_ms_daq_daq_sm.vhd index fbc493e..919d73f 100644 --- a/hdl/psi_ms_daq_daq_sm.vhd +++ b/hdl/psi_ms_daq_daq_sm.vhd @@ -576,11 +576,12 @@ begin if (unsigned(r.TfDoneCnt) /= 0) and (IrqFifoEmpty = '0') then v.IrqFifoRead := '1'; v.TfDoneCnt := std_logic_vector(unsigned(v.TfDoneCnt) - 1); - -- Generate IRQ if required - if IrqFifoGenIrq = '1' then - v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1'; - v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5)); - end if; + end if; + + -- Generate IRQ if required + if IrqFifoGenIrq = '1' and r.IrqFifoRead = '1' then + v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1'; + v.StrLastWin(to_integer(unsigned(IrqFifoStream))) := std_logic_vector(resize(unsigned(IrqLastWinNr), 5)); end if; -- *** Assign to signal ***