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base: AEK_8220_Libraries:2.3
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AEK_8220_Libraries:master AEK_8220_Libraries:latency_measure AEK_8220_Libraries:hipa_debug AEK_8220_Libraries:latfix AEK_8220_Libraries:develop AEK_8220_Libraries:version3
AEK_8220_Libraries:2.3 AEK_8220_Libraries:2.2 AEK_8220_Libraries:2.1
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compare: AEK_8220_Libraries:hipa_debug
Branches Tags
AEK_8220_Libraries:master AEK_8220_Libraries:latency_measure AEK_8220_Libraries:hipa_debug AEK_8220_Libraries:latfix AEK_8220_Libraries:develop AEK_8220_Libraries:version3
AEK_8220_Libraries:2.3 AEK_8220_Libraries:2.2 AEK_8220_Libraries:2.1

14 Commits
2.3 ... hipa_debug

Author SHA1 Message Date
stef_b
a68b5e6bba EVR STABLE: add generic to discard for hipa this statement EVR STABLE 2020-09-14 16:30:33 +02:00
stef_b
3049e28ea7 CDC: add cdc from tmem to decoder 2020-09-14 08:45:51 +02:00
stef_b
f440f95c8d debug: chipscope 2020-09-10 15:04:03 +02:00
stef_b
8f830624c0 DEBUG: add mgt more output on top for debug 2020-09-08 15:04:50 +02:00
stef_b
95a88cbba0 FEATURES: Add reset at the output of the ifc1210 wrapper 2020-09-02 08:30:00 +02:00
stef_b
287bfde2e0 FEATURE: Add SWAP generic to filter and correct TB accordingly 2020-01-31 13:58:41 +01:00
stef_b
3f1b7acc50 DEVEL: filter modification based on address decoding 2020-01-28 13:15:06 +01:00
stef_b
fdcadda6ed FEATURE: evr320 filter input address settable 
DOC: Correct address map for pulse length & delay
 2020-01-23 07:27:41 +01:00
stef_b
0d6457cb77 BIGFIX: For simu initialize delay value to 0 2019-12-13 14:34:37 +01:00
stef_b
83a4435e41 BUGFIX: std_logic_vector -> std_logic at output of delay (0) 2019-12-12 18:27:50 +01:00
stef_b
b77484c659 UPDATE: update due to delay modification 2019-12-11 16:28:26 +01:00
stef_b
071cf50ded DPDCY: due to change in PSI_COMMON suffix 2 -> cfg in ifc1210 wrapper 2019-12-02 15:12:31 +01:00
stef_b
5a060a160c FEATURE: add to TMEM interface regiter width & delay 2019-11-29 15:13:46 +01:00
stef_b
6b1f4fbcbc FEATUE: Modify delay & width as registers 2019-11-29 11:48:12 +01:00
13 changed files with 7276 additions and 6323 deletions
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doc/evr320.pdf
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doc/evr320.rtf
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doc/evr320.vsd
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122
hdl/evr320_data_filter.vhd
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@@ -4,65 +4,89 @@
-- Project: evr320
-- Authors: Jonas Purtschert
-- Description: Filter a specific data field from data buffer stream of the decoder:
-- Modif: Benoit Stef
-- not based on counter anymore but map to LSB into a generic array
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use work.psi_common_math_pkg.all;
entity evr320_data_filter is
generic (
ADDRESS : std_logic_vector(11 downto 0);
NUM_BYTES : integer := 8
);
port (
-- User stream interface
i_stream_clk : in std_logic; -- user clock
i_stream_data : in std_logic_vector(7 downto 0);
i_stream_addr : in std_logic_vector(10 downto 0);
i_stream_valid : in std_logic;
-- filter output:
o_data : out std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
o_valid : out std_logic := '0'
);
end evr320_data_filter;
generic (NUM_BYTES : integer := 8;
SWAP : boolean := false ); -- if true byte are swpped at output
port ( -- User stream interface
i_stream_clk : in std_logic; -- user clock
i_stream_data : in std_logic_vector(7 downto 0);
i_stream_addr : in std_logic_vector(10 downto 0);
i_stream_valid : in std_logic;
i_address : in std_logic_vector(11 downto 0);
-- filter output:
o_data : out std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
o_valid : out std_logic := '0'
);
end entity;
architecture behavioral of evr320_data_filter is
signal data_shift : std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
signal match : std_logic := '0';
signal shift_cnt : integer range 0 to NUM_BYTES;
-- array to store data value prior to map to output
type byte_array_t is array (NUM_BYTES-1 downto 0) of std_logic_vector(i_stream_data'range);
signal table_s : byte_array_t;
--pipe help
signal addr_dff_s : std_logic_vector(10 downto 0) := (others=>'0');
signal data_dff_s : std_logic_vector(i_stream_data'range) := (others=>'0');
signal filt_dff_s : std_logic_vector(i_address'range);
--helper
constant low_bd_c : integer := log2ceil(NUM_BYTES); --compute LSB for address decoding
signal ena_s : std_logic_vector(1 downto 0); --clock enable vector
begin
process(i_stream_clk)
variable addr : std_logic_vector(10 downto 0) := (others=>'0');
variable data : std_logic_vector(7 downto 0) := (others=>'0');
p : process(i_stream_clk)
begin
if (rising_edge(i_stream_clk)) then
o_valid <= '0';
if (rising_edge(i_stream_clk)) then
--*** 1st pipe stage ***
ena_s(0) <= i_stream_valid;
filt_dff_s <= i_address;
if (i_stream_valid = '1') then
addr := i_stream_addr;
data := i_stream_data;
if (addr = ADDRESS(10 downto 0) or match = '1') then
match <= '1';
if (shift_cnt < NUM_BYTES) then
data_shift <= data_shift((data_shift'high - data'length) downto 0) & data;
shift_cnt <= shift_cnt + 1;
else -- all data fetched, send to out
match <= '0';
shift_cnt <= 0;
o_valid <= '1';
o_data <= data_shift;
end if;
end if; -- if addr match
end if; -- if valid
addr_dff_s <= i_stream_addr;
data_dff_s <= i_stream_data;
end if;
--*** filling the array ***
if ena_s(0) = '1' then
if addr_dff_s(10 downto low_bd_c) = filt_dff_s(10 downto low_bd_c) then
--*** spatial loop ***
ena_s(1) <= '1';
for i in 0 to NUM_BYTES-1 loop
if addr_dff_s(low_bd_c-1 downto 0) = to_uslv(i,low_bd_c) then
table_s(i) <= data_dff_s ;
end if;
end loop;
end if;
else
ena_s(1) <= '0';
end if;
--*** set the output & valid accordingly***
if ena_s(1) = '1' then
if (from_uslv(addr_dff_s) = (from_uslv(filt_dff_s) + NUM_BYTES -1)) then
o_valid <= '1';
--*** spatial loop map output ***
for i in 0 to NUM_BYTES-1 loop
if SWAP then
o_data(NUM_BYTES+i*NUM_BYTES-1 downto 0+i*NUM_BYTES) <= table_s(NUM_BYTES-1-i);
else
o_data(NUM_BYTES+i*NUM_BYTES-1 downto 0+i*NUM_BYTES) <= table_s(i);
end if;
end loop;
else
o_valid <= '0';
end if;
end if;
end if;
end process;
end behavioral;
end architecture;

41
hdl/evr320_decoder.vhd
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@@ -24,8 +24,10 @@ use work.evr320_pkg.all;
entity evr320_decoder is
generic
(
FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
EVENT_RECORDER : boolean := false;
MEM_DATA_WIDTH : integer := 32
MEM_DATA_WIDTH : integer := 32;
EXP_REC_CLK_FREQ : natural := 142_800_000 -- in Hz
);
port
(
@@ -73,6 +75,7 @@ architecture behavioral of evr320_decoder is
-----------------------------------------------------------------------------
-- Constant
-----------------------------------------------------------------------------
--
constant HIGH : std_logic := '1';
constant LOW : std_logic := '0';
constant LOW_slv : std_logic_vector(15 downto 0) := (others => '0');
@@ -221,7 +224,9 @@ architecture behavioral of evr320_decoder is
-- attribute fsm_safe_state : string;
-- attribute fsm_safe_state of frame_fsm : signal is "default_state";
-- attribute fsm_safe_state of mem_fsm : signal is "default_state";
constant evr_stable_time_int_c : natural := EXP_REC_CLK_FREQ/100;
constant evr_stable_time_slv_c : std_logic_vector(cs_timeout_cnt'range):= std_logic_vector(to_unsigned(evr_stable_time_int_c, cs_timeout_cnt'length));
begin
-----------------------------------------------------------------------------
@@ -230,9 +235,10 @@ begin
debug_clk <= i_mgt_rx_clk;
debug( 15 downto 0) <= i_mgt_rx_data;
debug( 17 downto 16) <= i_mgt_rx_charisk;
debug( 23 downto 18) <= (others=>'0');
debug( 31 downto 24) <= (others => '0');
debug( 35 downto 32) <= "0001" when (frame_fsm = frame_idle ) else
debug(18) <= evr_stable;--new
debug(26 downto 19) <= i_evr_params.event_numbers(1);
debug(34 downto 27) <= i_evr_params.event_numbers(2);
debug(38 downto 35) <= "0001" when (frame_fsm = frame_idle ) else
"0010" when (frame_fsm = frame_addr_gap) else
"0011" when (frame_fsm = frame_addr ) else
"0100" when (frame_fsm = frame_data_gap) else
@@ -242,7 +248,7 @@ begin
"1000" when (frame_fsm = frame_chk2_gap) else
"1001" when (frame_fsm = frame_chk2 ) else
"0000";
debug( 39 downto 36) <= (others => '0');
debug( 39) <= '0';
debug( 40) <= usr_events( 0)( 3);
debug( 41) <= usr_events( 1)( 3);
debug( 42) <= usr_events( 2)( 3);
@@ -267,7 +273,7 @@ begin
end generate dbg_evt_rec;
dbg_no_evt_rec: if not(EVENT_RECORDER) generate
debug(127 downto 64) <= (others => '0');
end generate dbg_no_evt_rec;
@@ -289,6 +295,7 @@ begin
-----------------------------------------------------------------------------
-- evr stable state
-- TODO: Perform the sync according to k28.5
-----------------------------------------------------------------------------
prc_evr_stable : process(i_mgt_rx_clk)
begin
@@ -296,9 +303,9 @@ begin
if (i_mgt_rst = '1') then
evr_stable <= '0';
else
if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and
(std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and
(std_logic_vector(cs_timeout_cnt) < X"15CA20")) then
if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and
(std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and
(std_logic_vector(cs_timeout_cnt) < evr_stable_time_slv_c)) then -- make generics depending on recovery_clock
evr_stable <= '1';
else
evr_stable <= '0';
@@ -317,13 +324,21 @@ begin
if (i_mgt_rst = '1') then
usr_events <= (others => (others => '0'));
else
for i in 0 to 3 loop
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i)) and (evr_stable = '1')) then
for i in 0 to 3 loop
if FACILITY = "HIPA" then
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i))) then
usr_events(i) <= "1111";
else
usr_events(i) <= usr_events(i)( 2 downto 0) & '0';
end if;
end loop;
else
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i))and (evr_stable = '1')) then
usr_events(i) <= "1111";
else
usr_events(i) <= usr_events(i)( 2 downto 0) & '0';
end if;
end if;
end loop;
end if;
end if;
end process;

684
hdl/evr320_ifc1210_wrapper.vhd
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@@ -2,7 +2,7 @@
-- Paul Scherrer Institute (PSI)
-- ---------------------------------------------------------------------------
-- Unit : evr320_ifc1210_wrapper.vhd
-- Author : Patric Bucher
-- Author : Patric Bucher, Benoit Stef
-- ---------------------------------------------------------------------------
-- Copyright© PSI, Section DSV
-- ---------------------------------------------------------------------------
@@ -20,371 +20,379 @@ use work.evr320_pkg.all;
use work.v6vlx_gtxe1_pkg.all;
entity evr320_ifc1210_wrapper is
generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000; -- Xuser Clk Frequency in Hz
g_EVT_DURATION : typ_arr_pos := (1, 1, 1, 1, 1); -- output extend in clock recovery clock cycles event 0,1,2,3
g_EVT_HOLDOFF : typ_arr_nat := (0, 0, 0, 0, 0); -- Minimum number of clock cycles between input pulses event sos,0,1,2,3
g_EVT_DELAY : typ_arr_pos := (4, 4, 4, 4, 4) -- delay in recovery clock cycles event sos,0,1,2,3
);
port(
tick1sec_i : in std_logic;
-- ------------------------------------------------------------------------
-- Debug interface
-- ------------------------------------------------------------------------
debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0);
-- ------------------------------------------------------------------------
-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
-- ------------------------------------------------------------------------
xuser_CLK : in std_logic;
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector(7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay
sos_event_o : out std_logic; -- Start-of-Sequence Event
-- new features adjusted in delay & length
usr_events_adj_o : out std_logic_vector(3 downto 0); -- User defined event pulses adjusted in delay & length
sos_events_adj_o : out std_logic; -- Start-of-Sequence adjusted in delay & length
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
);
generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz
);
port(
-- ------------------------------------------------------------------------
-- Debug interface
-- ------------------------------------------------------------------------
debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0);
-- ------------------------------------------------------------------------
-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
-- ------------------------------------------------------------------------
xuser_CLK : in std_logic;
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector(7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
mgt_rx_data_o : out std_logic_Vector(15 downto 0); -- for debug purpose
mgt_rx_charisk_o : out std_logic_vector(1 downto 0); -- for debug purpose
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
rst_evr_o : out std_logic; -- reset according to RX Loss of sync
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay
sos_event_o : out std_logic; -- Start-of-Sequence Event
usr_events_adj_o : out std_logic_vector(3 downto 0); -- User defined event pulses adjusted in delay & length
sos_events_adj_o : out std_logic; -- Start-of-Sequence adjusted in delay & length
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
);
end evr320_ifc1210_wrapper;
architecture rtl of evr320_ifc1210_wrapper is
-- --------------------------------------------------------------------------
-- Parameters
-- --------------------------------------------------------------------------
constant c_TOSCA2_DATA_WIDTH : integer := 64;
constant c_EVR_REG64_COUNT : integer := 16; -- unused, only documentation
constant c_EVR_MEM_SIZE : integer := 16384; -- unused, only documentation
-- --------------------------------------------------------------------------
-- Parameters
-- --------------------------------------------------------------------------
constant c_TOSCA2_DATA_WIDTH : integer := 64;
constant c_EVR_REG64_COUNT : integer := 16; -- unused, only documentation
constant c_EVR_MEM_SIZE : integer := 16384; -- unused, only documentation
-- --------------------------------------------------------------------------
-- Signal definitions
-- --------------------------------------------------------------------------
signal clk_evr : std_logic;
--signal clk_evr_monitor : std_logic; -- for debugging
signal rst_evr : std_logic;
signal mgt_control : std_logic_vector(31 downto 0) := (others => '0');
signal mgt_status : std_logic_vector(31 downto 0);
signal mgt_rx_data : std_logic_vector(15 downto 0);
signal mgt_rx_charisk : std_logic_vector(1 downto 0);
signal mgt_lossofsync : std_logic;
signal mgt_reset_tmem_evr : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
signal mem_clk : std_logic;
signal mem_addr_evr : std_logic_vector(11 downto 0);
signal mem_addr_tosca : std_logic_vector(10 downto 0);
signal mem_data : std_logic_vector(c_TOSCA2_DATA_WIDTH - 1 downto 0);
signal evr_params : typ_evr320_params;
signal evr_params_sync : typ_evr320_params;
signal evr_params_xuser : typ_evr320_params;
signal event_recorder_status : typ_evt_rec_status;
signal event_recorder_control : typ_evt_rec_ctrl;
signal event_recorder_control_sync : typ_evt_rec_ctrl;
signal event_recorder_control_xuser : typ_evt_rec_ctrl;
signal evr_latency_measure_stat : typ_rec_latency_measure_stat;
signal evr_latency_measure_ctrl : typ_rec_latency_measure_ctrl;
signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0');
signal debug_data : std_logic_vector(127 downto 0);
signal decoder_event_valid : std_logic;
signal decoder_event : std_logic_vector(7 downto 0);
-- --------------------------------------------------------------------------
-- Signal definitions
-- --------------------------------------------------------------------------
signal clk_evr : std_logic;
--signal clk_evr_monitor : std_logic; -- for debugging
signal rst_evr : std_logic;
signal mgt_control : std_logic_vector(31 downto 0) := (others => '0');
signal mgt_status : std_logic_vector(31 downto 0);
signal mgt_rx_data : std_logic_vector(15 downto 0);
signal mgt_rx_charisk : std_logic_vector(1 downto 0);
signal mgt_lossofsync : std_logic;
signal mgt_reset_tmem_evr : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
signal mem_clk : std_logic;
signal mem_addr_evr : std_logic_vector(11 downto 0);
signal mem_addr_tosca : std_logic_vector(10 downto 0);
signal mem_data : std_logic_vector(c_TOSCA2_DATA_WIDTH - 1 downto 0);
signal evr_params : typ_evr320_params;
signal evr_params_sync : typ_evr320_params;
signal evr_params_xuser : typ_evr320_params;
signal event_recorder_status : typ_evt_rec_status;
signal event_recorder_control : typ_evt_rec_ctrl;
signal event_recorder_control_sync : typ_evt_rec_ctrl;
signal event_recorder_control_xuser : typ_evt_rec_ctrl;
signal evr_latency_measure_stat : typ_rec_latency_measure_stat;
signal evr_latency_measure_ctrl : typ_rec_latency_measure_ctrl;
signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0');
signal debug_data : std_logic_vector(127 downto 0);
signal decoder_event_valid : std_logic;
signal decoder_event : std_logic_vector(7 downto 0);
-- --------------------------------------------------------------------------
-- Attribute definitions
-- --------------------------------------------------------------------------
attribute keep : string;
attribute keep of clk_evr : signal is "TRUE";
attribute keep of debug_data : signal is "TRUE";
signal usr_events_s : std_logic_vector(3 downto 0);
signal sos_event_s : std_logic;
-- --------------------------------------------------------------------------
-- Attribute definitions
-- --------------------------------------------------------------------------
attribute keep : string;
attribute keep of clk_evr : signal is "TRUE";
attribute keep of debug_data : signal is "TRUE";
signal usr_events_s : std_logic_vector(3 downto 0);
signal sos_event_s : std_logic;
signal evr_rst_s : std_logic;
signal usr_event_delay_s : typ_arr_delay;
signal usr_event_width_s : typ_arr_width;
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- //////////////////// Main Body /////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- //////////////////// Main Body /////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
begin
-- --------------------------------------------------------------------------
-- static signal assignments
-- --------------------------------------------------------------------------
mgt_lossofsync <= mgt_status(15);
rst_evr <= mgt_status(15);
mem_addr_evr <= '0' & mem_addr_tosca;
-- --------------------------------------------------------------------------
-- static signal assignments
-- --------------------------------------------------------------------------
mgt_lossofsync <= mgt_status(15);
rst_evr_o <= mgt_status(15);
mem_addr_evr <= '0' & mem_addr_tosca;
mgt_control(c_GTXRESET) <= mgt_control_i(c_GTXRESET) or mgt_sfp_los_i or mgt_reset_tmem_evr;
mgt_control(4 downto 1) <= mgt_control_i(4 downto 1);
mgt_control(c_RXCDRRESET) <= mgt_control_i(c_RXCDRRESET);
mgt_control(31 downto 6) <= mgt_control_i(31 downto 6);
mgt_control(c_GTXRESET) <= mgt_control_i(c_GTXRESET) or mgt_sfp_los_i or mgt_reset_tmem_evr;
mgt_control(4 downto 1) <= mgt_control_i(4 downto 1);
mgt_control(c_RXCDRRESET) <= mgt_control_i(c_RXCDRRESET);
mgt_control(31 downto 6) <= mgt_control_i(31 downto 6);
-- --------------------------------------------------------------------------
-- Synchronisation to EVR Clock
-- --------------------------------------------------------------------------
prc_sync_evr : process(clk_evr)
begin
if rising_edge(clk_evr) then
---
evr_params_sync <= evr_params_xuser;
evr_params <= evr_params_sync;
---
event_recorder_control_sync <= event_recorder_control_xuser;
event_recorder_control <= event_recorder_control_sync;
---
end if;
end process;
-- --------------------------------------------------------------------------
-- Synchronisation to EVR Clock
-- --------------------------------------------------------------------------
prc_sync_evr : process(clk_evr)
begin
if rising_edge(clk_evr) then
---
evr_params_sync <= evr_params_xuser;
evr_params <= evr_params_sync;
---
event_recorder_control_sync <= event_recorder_control_xuser;
event_recorder_control <= event_recorder_control_sync;
---
end if;
end process;
-- --------------------------------------------------------------------------
-- EVR320 Decoder
-- --------------------------------------------------------------------------
evr320_decoder_inst : entity work.evr320_decoder
generic map(
EVENT_RECORDER => g_EVENT_RECORDER,
MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH)
port map(
-- Debug interface
debug_clk => debug_clk,
debug => debug_data,
-- GTX parallel interface
i_mgt_rst => mgt_lossofsync,
i_mgt_rx_clk => clk_evr,
i_mgt_rx_data => mgt_rx_data,
i_mgt_rx_charisk => mgt_rx_charisk,
-- User interface CPU clock
i_usr_clk => mem_clk,
i_evr_params => evr_params,
o_event_recorder_stat => event_recorder_status,
i_event_recorder_ctrl => event_recorder_control,
i_mem_addr => mem_addr_evr,
o_mem_data => mem_data,
-- user stream interface, user clock
i_stream_clk => stream_clk_i,
o_stream_data => stream_data_o,
o_stream_addr => stream_addr_o,
o_stream_valid => stream_valid_o,
-- User interface MGT clock
o_usr_events => usr_events_s,
-- o_usr_events_ext => usr_events_ext_o, -- not in use anymore
o_sos_event => sos_event_s,
o_event => decoder_event,
o_event_valid => decoder_event_valid
);
-- --------------------------------------------------------------------------
-- EVR320 Decoder
-- --------------------------------------------------------------------------
evr320_decoder_inst : entity work.evr320_decoder
generic map(
FACILITY => g_FACILITY,
EVENT_RECORDER => g_EVENT_RECORDER,
MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH,
EXP_REC_CLK_FREQ => 50_632_820)
port map(
-- Debug interface
debug_clk => debug_clk,
debug => debug_data,
-- GTX parallel interface
i_mgt_rst => mgt_lossofsync,
i_mgt_rx_clk => clk_evr,
i_mgt_rx_data => mgt_rx_data,
i_mgt_rx_charisk => mgt_rx_charisk,
-- User interface CPU clock
i_usr_clk => mem_clk,
i_evr_params => evr_params,
o_event_recorder_stat => event_recorder_status,
i_event_recorder_ctrl => event_recorder_control,
i_mem_addr => mem_addr_evr,
o_mem_data => mem_data,
-- user stream interface, user clock
i_stream_clk => stream_clk_i,
o_stream_data => stream_data_o,
o_stream_addr => stream_addr_o,
o_stream_valid => stream_valid_o,
-- User interface MGT clock
o_usr_events => usr_events_s,
-- o_usr_events_ext => usr_events_ext_o, -- not in use anymore
o_sos_event => sos_event_s,
o_event => decoder_event,
o_event_valid => decoder_event_valid
);
usr_events_o <= usr_events_s;
sos_event_o <= sos_event_s;
usr_events_o <= usr_events_s;
sos_event_o <= sos_event_s;
-- --------------------------------------------------------------------------
-- MGT Wrapper for GTX Virtex-6
-- --------------------------------------------------------------------------
mgt_wrapper_inst : entity work.v6vlx_gtxe1_wrapper
generic map(
g_MGT_LOCATION => g_MGT_LOCATION,
g_FACILITY => g_FACILITY)
port map(
-- MGT serial interface
i_mgt_refclk => mgt_refclk_i,
o_mgt_refclk => open,
i_mgt_rx_p => mgt_rx_p,
i_mgt_rx_n => mgt_rx_n,
o_mgt_tx_p => mgt_tx_p,
o_mgt_tx_n => mgt_tx_n,
-- MGT parallel interface
o_mgt_status => mgt_status,
i_mgt_control => mgt_control,
o_mgt_recclk => clk_evr,
o_mgt_rx_data => mgt_rx_data,
o_mgt_rx_charisk => mgt_rx_charisk
);
-- --------------------------------------------------------------------------
-- MGT Wrapper for GTX Virtex-6
-- --------------------------------------------------------------------------
mgt_wrapper_inst : entity work.v6vlx_gtxe1_wrapper
generic map(
g_MGT_LOCATION => g_MGT_LOCATION,
g_FACILITY => g_FACILITY)
port map(
-- MGT serial interface
i_mgt_refclk => mgt_refclk_i,
o_mgt_refclk => open,
i_mgt_rx_p => mgt_rx_p,
i_mgt_rx_n => mgt_rx_n,
o_mgt_tx_p => mgt_tx_p,
o_mgt_tx_n => mgt_tx_n,
-- MGT parallel interface
o_mgt_status => mgt_status,
i_mgt_control => mgt_control,
o_mgt_recclk => clk_evr,
o_mgt_rx_data => mgt_rx_data,
o_mgt_rx_charisk => mgt_rx_charisk
);
mgt_rx_charisk_o <= mgt_rx_charisk;
mgt_rx_data_o <= mgt_rx_data;
-- --------------------------------------------------------------------------
-- TMEM
-- --------------------------------------------------------------------------
--formatter:off
evr320_tmem_inst : entity work.evr320_tmem
port map(
-- TOSCA2 TMEM Interface
xuser_CLK => xuser_CLK,
xuser_RESET => xuser_RESET,
xuser_TMEM_ENA => xuser_TMEM_ENA,
xuser_TMEM_WE => xuser_TMEM_WE,
xuser_TMEM_ADD => xuser_TMEM_ADD,
xuser_TMEM_DATW => xuser_TMEM_DATW,
xuser_TMEM_DATR => xuser_TMEM_DATR,
-- EVR320 Memory/Parameter Interface
evr_params_o => evr_params_xuser,
evr_frequency_i => evr_frequency,
evr_evt_rec_status_i => event_recorder_status,
evr_evt_rec_control_o => event_recorder_control_xuser,
evr_latency_measure_stat_i => evr_latency_measure_stat,
evr_latency_measure_ctrl_o => evr_latency_measure_ctrl,
mgt_status_i => mgt_status,
mgt_reset_o => mgt_reset_tmem_evr,
mem_clk_o => mem_clk,
mem_addr_o => mem_addr_tosca,
mem_data_i => mem_data,
--
evr_clk_i => clk_evr,
evr_rst_i => evr_rst_s,
evr_pulse_delay_o => usr_event_delay_s,
evr_pulse_width_o => usr_event_width_s);
-- --------------------------------------------------------------------------
-- TMEM
-- --------------------------------------------------------------------------
evr320_tmem_inst : entity work.evr320_tmem
port map(
-- TOSCA2 TMEM Interface
xuser_CLK => xuser_CLK,
xuser_RESET => xuser_RESET,
xuser_TMEM_ENA => xuser_TMEM_ENA,
xuser_TMEM_WE => xuser_TMEM_WE,
xuser_TMEM_ADD => xuser_TMEM_ADD,
xuser_TMEM_DATW => xuser_TMEM_DATW,
xuser_TMEM_DATR => xuser_TMEM_DATR,
-- EVR320 Memory/Parameter Interface
evr_params_o => evr_params_xuser,
evr_frequency_i => evr_frequency,
evr_evt_rec_status_i => event_recorder_status,
evr_evt_rec_control_o => event_recorder_control_xuser,
evr_latency_measure_stat_i => evr_latency_measure_stat,
evr_latency_measure_ctrl_o => evr_latency_measure_ctrl,
mgt_status_i => mgt_status,
mgt_reset_o => mgt_reset_tmem_evr,
mem_clk_o => mem_clk,
mem_addr_o => mem_addr_tosca,
mem_data_i => mem_data
);
-- --------------------------------------------------------------------------
-- Measure EVR Clock (based on xuser_CLK)
-- --------------------------------------------------------------------------
clock_meas_inst : entity work.psi_common_clk_meas
generic map(
MasterFrequency_g => g_XUSER_CLK_FREQ,
MaxMeasFrequency_g => 150000000
)
port map(
ClkMaster => xuser_CLK,
Rst => xuser_RESET,
ClkTest => clk_evr,
FrequencyHz => evr_frequency
);
-- --------------------------------------------------------------------------
-- Measure EVR Clock (based on xuser_CLK)
-- --------------------------------------------------------------------------
clock_meas_inst : entity work.psi_common_clk_meas
generic map(
MasterFrequency_g => g_XUSER_CLK_FREQ,
MaxMeasFrequency_g => 150000000
)
port map(
ClkMaster => xuser_CLK,
Rst => xuser_RESET,
ClkTest => clk_evr,
FrequencyHz => evr_frequency
);
-- --------------------------------------------------------------------------
-- Event Latency Measurement for SW tests
-- --------------------------------------------------------------------------
lat_meas_block : block
type state_type is (armed, count);
signal state : state_type;
signal counter : unsigned(31 downto 0);
signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
signal event_detected : std_logic_vector(3 downto 0);
signal event_detected_sync : std_logic_vector(1 downto 0);
constant MAX_COUNT : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 10, 32); -- MAX 100ms ~ 10Hz
begin
-- --------------------------------------------------------------------------
-- Event Latency Measurement for SW tests
-- --------------------------------------------------------------------------
lat_meas_block : block
type state_type is (armed, count);
signal state : state_type;
signal counter : unsigned(31 downto 0);
signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
signal event_detected : std_logic_vector(3 downto 0);
signal event_detected_sync : std_logic_vector(1 downto 0);
constant MAX_COUNT : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 100, 32); -- MAX 10ms
begin
-- Process: filter events for matching event_nr register:
---------------------------------------------------------
ext_event_proc : process(clk_evr)
begin
if (rising_edge(clk_evr)) then
-- sync to MGT clock domain:
event_nr_sync <= evr_latency_measure_ctrl.event_nr;
event_nr <= event_nr_sync;
-- Process: filter events for matching event_nr register:
---------------------------------------------------------
ext_event_proc : process(clk_evr)
begin
if (rising_edge(clk_evr)) then
-- sync to MGT clock domain:
event_nr_sync <= evr_latency_measure_ctrl.event_nr;
event_nr <= event_nr_sync;
-- check if event has been detected and stretch pulse:
event_detected <= event_detected(2 downto 0) & '0';
if (decoder_event_valid = '1' and decoder_event = event_nr) then
event_detected <= (others => '1');
end if;
end if;
end process;
-- check if event has been detected and stretch pulse:
event_detected <= event_detected(2 downto 0) & '0';
if (decoder_event_valid = '1' and decoder_event = event_nr) then
event_detected <= (others => '1');
end if;
end if;
end process;
-- Process: Counter when configured event has been detected:
------------------------------------------------------------
lat_meas_proc : process(xuser_CLK, counter)
begin
if rising_edge(xuser_CLK) then
-- sync to user clock domain:
event_detected_sync <= event_detected_sync(0) & event_detected(3);
-- Process: Counter when configured event has been detected:
------------------------------------------------------------
lat_meas_proc : process(xuser_CLK, counter)
begin
if rising_edge(xuser_CLK) then
-- sync to user clock domain:
event_detected_sync <= event_detected_sync(0) & event_detected(3);
-- counter FSM:
---------------
case state is
-- counter is armed:
when armed =>
counter <= (others => '0');
-- start counting when event detected (rising edge):
if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
state <= count;
end if;
-- counter FSM:
---------------
case state is
-- counter is armed:
when armed =>
counter <= (others => '0');
-- start counting when event detected (rising edge):
if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
state <= count;
end if;
-- counting:
when count =>
-- count only up to 10ms, and stop:
if (counter < MAX_COUNT) then
counter <= counter + 1;
end if;
if (evr_latency_measure_ctrl.counter_arm = '1') then
state <= armed;
end if;
end case;
end if;
-- counting:
when count =>
-- count only up to 10ms, and stop:
if (counter < MAX_COUNT) then
counter <= counter + 1;
end if;
if (evr_latency_measure_ctrl.counter_arm = '1') then
state <= armed;
end if;
end case;
end if;
evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
end process;
evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
end process;
end block;
end block;
-- --------------------------------------------------------------------------
-- Add delay output
-- --------------------------------------------------------------------------
output_delay_block : block
--signal rst0_s, rst1_s : std_logic; -- double stage sync for reset
signal usr_evt_shaped_s : std_logic_vector(4 downto 0);
signal usr_events_adj_s : std_logic_vector(4 downto 0);
signal usr_events_concat_s : std_logic_vector(4 downto 0);
-- --------------------------------------------------------------------------
-- Add delay output
-- --------------------------------------------------------------------------
output_delay_block : block
signal rst0_s, rst1_s : std_logic; -- double stage sync for reset
signal usr_evt_shaped_s : std_logic_vector(4 downto 0);
signal usr_events_adj_s : std_logic_vector(4 downto 0);
signal usr_events_concat_s : std_logic_vector(4 downto 0);
begin
--*** double stage sync for reset ***--
proc_rst : process(clk_evr)
begin
if rising_edge(clk_evr) then
rst0_s <= xuser_RESET;
rst1_s <= rst0_s;
end if;
end process;
begin
evr_rst_s <= mgt_status(15); -- RXLOSSOFSYNC
usr_events_concat_s <= usr_events_s & sos_event_s;
usr_events_concat_s <= usr_events_s & sos_event_s;
gene_adj_out : for i in 0 to 4 generate
--*** Adjust pulse length in clk cycles EVENT 0,1,2,3 ***
inst_pulslength_evt0 : entity work.psi_common_pulse_shaper
generic map(Duration_g => g_EVT_DURATION(i),
HoldIn_g => false,
HoldOff_g => g_EVT_HOLDOFF(i))
port map(Clk => clk_evr,
Rst => rst1_s,
InPulse => usr_events_concat_s(i),
OutPulse => usr_evt_shaped_s(i));
gene_adj_out : for i in 0 to 4 generate
--*** delay adjust EVENT 0,1,2,3***
inst_adjdelay_evt0 : entity work.psi_common_delay
generic map(Width_g => 1,
Delay_g => g_EVT_DELAY(i),
Resource_g => "AUTO",
BramThreshold_g => 128,
RstState_g => True,
RamBehavior_g => "RBW")
port map(Clk => clk_evr,
Rst => rst1_s,
InData(0) => usr_evt_shaped_s(i),
InVld => '1',
OutData(0)=> usr_events_adj_s(i));
end generate;
--*** Adjust pulse length in clk cycles EVENT 0,1,2,3 ***
inst_pulslength_evt0 : entity work.psi_common_pulse_shaper_cfg
generic map(HoldIn_g => false,
HoldOffEna_g => false,
MaxHoldOff_g => 10,
MaxDuration_g => MaxDuration_c,
RstPol_g => '1')
port map(clk_i => clk_evr,
rst_i => evr_rst_s,
width_i => usr_event_width_s(i),
hold_i => (others => '0'),
dat_i => usr_events_concat_s(i),
dat_o => usr_evt_shaped_s(i));
usr_events_adj_o <= usr_events_adj_s(4 downto 1);
sos_events_adj_o <= usr_events_adj_s(0);
end block;
-- --------------------------------------------------------------------------
-- port mapping
-- --------------------------------------------------------------------------
clk_evr_o <= clk_evr;
mgt_status_o <= mgt_status;
debug <= debug_data;
--*** delay adjust EVENT 0,1,2,3***
inst_adjdelay_evt0 : entity work.psi_common_delay_cfg
generic map(Width_g => 1,
MaxDelay_g => MaxDelay_c,
RStPol_g => '1',
RamBehavior_g => "RBW",
Hold_g => True)
port map( clk_i => clk_evr,
rst_i => evr_rst_s,
dat_i(0) => usr_evt_shaped_s(i),
str_i => '1',
del_i => usr_event_delay_s(i),
dat_o(0) => usr_events_adj_s(i));
end generate;
usr_events_adj_o <= usr_events_adj_s(4 downto 1);
sos_events_adj_o <= usr_events_adj_s(0);
end block;
-- --------------------------------------------------------------------------
-- port mapping
-- --------------------------------------------------------------------------
clk_evr_o <= clk_evr;
mgt_status_o <= mgt_status;
debug <= debug_data;
end rtl;
-- ----------------------------------------------------------------------------

9
hdl/evr320_pkg.vhd
View File

@@ -12,6 +12,7 @@
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.psi_common_math_pkg.all;
package evr320_pkg is
@@ -61,9 +62,11 @@ package evr320_pkg is
counter_val : std_logic_vector(31 downto 0);
end record;
type typ_arr_nat is array (4 downto 0) of natural;
type typ_arr_pos is array (4 downto 0) of positive;
--*** Type record and constant for new feature pulse width & delay ***
constant MaxDuration_c : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles
constant MaxDelay_c : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles
type typ_arr_width is array (4 downto 0) of std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0);
type typ_arr_delay is array (4 downto 0) of std_logic_vector(log2ceil(MaxDelay_c)-1 downto 0);
-- --------------------------------------------------------------------------
-- Type Initialisation

139
hdl/evr320_tmem.vhd
View File

@@ -2,9 +2,9 @@
-- Paul Scherrer Institute (PSI)
-- ---------------------------------------------------------------------------
-- Unit : evr320_tmem.vhd
-- Author : Patric Bucher
-- Author : Patric Bucher, Benoit Stef
-- ---------------------------------------------------------------------------
-- Copyright© PSI, Section DSV
-- Copyright (c) PSI, Section DSV
-- ---------------------------------------------------------------------------
-- Comment : TMEM address decoding for register and memory access to evr320.
-- ---------------------------------------------------------------------------
@@ -18,7 +18,6 @@ use tosca2.tosca2_glb_pkg.all;
use work.evr320_pkg.all;
entity evr320_tmem is
port(
-- ------------------------------------------------------------------------
@@ -44,7 +43,14 @@ entity evr320_tmem is
mgt_reset_o : out std_logic;
mem_clk_o : out std_logic;
mem_addr_o : out std_logic_vector(10 downto 0);
mem_data_i : in std_logic_vector(63 downto 0)
mem_data_i : in std_logic_vector(63 downto 0);
---------------------------------------------------------------------------
-- EVR320 pulse output paremters
---------------------------------------------------------------------------
evr_clk_i : in std_logic;
evr_rst_i : in std_logic;
evr_pulse_delay_o : out typ_arr_delay;
evr_pulse_width_o : out typ_arr_width
);
end evr320_tmem;
@@ -104,7 +110,10 @@ architecture rtl of evr320_tmem is
-- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback
-- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0'));
-- event pulse config
signal evr_puls_width_cfg_s : typ_arr_width :=((others=>(others=>'0')));
signal evr_puls_delay_cfg_s : typ_arr_delay :=((others=>(others=>'0')));
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
@@ -122,6 +131,7 @@ begin
lat_counter_val <= evr_latency_measure_stat_i.counter_val;
-- --------------------------------------------------------------------------
-- TODO: proper CDC
-- Synchronisation to xuser_CLK
-- --------------------------------------------------------------------------
prc_sync_xuser: process (xuser_CLK)
@@ -165,6 +175,9 @@ begin
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
when X"A" => xuser_TMEM_DATR <= evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050
when X"B" => xuser_TMEM_DATR <= evr_puls_width_cfg_s(4) & evr_puls_width_cfg_s(3) & evr_puls_width_cfg_s(2) & evr_puls_width_cfg_s(1) ; --64 bit / ByteAddr 054
when X"C" => xuser_TMEM_DATR <= reserved(63 downto 32) & evr_puls_width_cfg_s(0) & evr_puls_delay_cfg_s(0); -- 64bit / ByteAddr 058
when others => xuser_TMEM_DATR <= (others => '0');
end case;
else --> 0x0080-0x4000
@@ -255,6 +268,24 @@ begin
if xuser_TMEM_WE_reg(7) = '1' and xuser_TMEM_DATW_reg(56) = '1' then er_error_ack <= (others => '1'); end if;
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"A" then --ByteAddr 050
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 del
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_delay_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 del
if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_delay_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 del
if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_delay_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 del
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"B" then --ByteAddr 058
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_width_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 width
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 width
if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_width_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 width
if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_width_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 width
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"C" then --ByteAddr 060
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(0) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- sos evt del
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(0) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- sos evt width
end if;
end if;
end if;
end process;
@@ -265,13 +296,107 @@ begin
-- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
--event recorder had to be also added to cdc
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
evr_latency_measure_ctrl_o <= (lat_event_nr, lat_counter_arm);
-- --------------------------------------------------------------------------
-- add CDC output
-- --------------------------------------------------------------------------
block_cdc_evr_puls_param : block
signal input_s, output_s : std_logic_vector(10 * 16 - 1 downto 0);
begin
-- ------------------------------------------------------------------------
-- Assemble Input
-- ------------------------------------------------------------------------
--** pulse delay parameters **
input_s(15 downto 0) <= evr_puls_delay_cfg_s(0);
input_s(31 downto 16) <= evr_puls_delay_cfg_s(1);
input_s(47 downto 32) <= evr_puls_delay_cfg_s(2);
input_s(63 downto 48) <= evr_puls_delay_cfg_s(3);
input_s(79 downto 64) <= evr_puls_delay_cfg_s(4);
--** pulse width parameters **
input_s(95 downto 80) <= evr_puls_width_cfg_s(0);
input_s(111 downto 96) <= evr_puls_width_cfg_s(1);
input_s(127 downto 112) <= evr_puls_width_cfg_s(2);
input_s(143 downto 128) <= evr_puls_width_cfg_s(3);
input_s(159 downto 144) <= evr_puls_width_cfg_s(4);
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(DataWidth_g => input_s'length)
port map(ClkA => xuser_CLK,
RstInA => xuser_RESET,
DataA => input_s,
ClkB => evr_clk_i,
RstInB => evr_rst_i,
DataB => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
--** pulse delay parameters **
evr_pulse_delay_o(0) <= output_s(15 downto 0);
evr_pulse_delay_o(1) <= output_s(31 downto 16);
evr_pulse_delay_o(2) <= output_s(47 downto 32);
evr_pulse_delay_o(3) <= output_s(63 downto 48);
evr_pulse_delay_o(4) <= output_s(79 downto 64);
--** pulse width parameters **
evr_pulse_width_o(0) <= output_s(95 downto 80);
evr_pulse_width_o(1) <= output_s(111 downto 96);
evr_pulse_width_o(2) <= output_s(127 downto 112);
evr_pulse_width_o(3) <= output_s(143 downto 128);
evr_pulse_width_o(4) <= output_s(159 downto 144);
end block;
block_cdc_evr_code_param : block
signal input_s, output_s : std_logic_vector(108 downto 0);
begin
-- ------------------------------------------------------------------------
-- Assemble Input
-- ------------------------------------------------------------------------
--** event numbers **
input_s( 7 downto 0) <= event_numbers(0);
input_s(15 downto 8) <= event_numbers(1);
input_s(23 downto 16) <= event_numbers(2);
input_s(31 downto 24) <= event_numbers(3);
--** event pulse enable **
input_s(35 downto 32) <= event_enable;
--** time counter **
input_s(67 downto 36) <= cs_min_time;
input_s(99 downto 68) <= cs_min_cnt;
--** latency counter **
input_s(100) <= lat_counter_arm;
input_s(108 downto 101) <= lat_event_nr;
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(DataWidth_g => input_s'length)
port map(ClkA => xuser_CLK,
RstInA => xuser_RESET,
RstOutA => open,
DataA => input_s,
ClkB => evr_clk_i,
RstInB => evr_rst_i,
RstOutB => open,
DataB => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
--** event numbers **
evr_params_o.event_numbers(0) <= output_s( 7 downto 0) ;
evr_params_o.event_numbers(1) <= output_s(15 downto 8) ;
evr_params_o.event_numbers(2) <= output_s(23 downto 16);
evr_params_o.event_numbers(3) <= output_s(31 downto 24);
--** event pulse enable **
evr_params_o.event_enable <= output_s(35 downto 32);
--** time counter **
evr_params_o.cs_min_time <= output_s(67 downto 36);
evr_params_o.cs_min_cnt <= output_s(99 downto 68);
--** latency counter **
evr_latency_measure_ctrl_o.counter_arm <= output_s(100) ;
evr_latency_measure_ctrl_o.event_nr <= output_s(108 downto 101) ;
end block;
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////

4
hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd
View File

@@ -7,7 +7,7 @@
-- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
-- Copyright<EFBFBD> PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz
------------------------------------------------------------------------------
@@ -384,7 +384,7 @@ begin
RXPLLLKDET => o_mgt.ctrl.RXPLLLKDET , --RXPLLLKDET_OUT,
RXPLLLKDETEN => '1', --
RXPLLPOWERDOWN => '0', --
RXPLLREFSELDY => "000", -- GREFCLKRX
RXPLLREFSELDY => "000", --GREFCLKRX
RXRATE => "00", --
RXRATEDONE => open, --
RXRESETDONE => o_mgt.ctrl.RXRESETDONE , --RXRESETDONE_OUT,

6
hdl/v6vlx_gtxe1_wrapper.vhd
View File

@@ -7,7 +7,7 @@
-- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
-- Copyright<EFBFBD> PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment : Wrapper vor Virtex-6 GTX ready to use in HIPA and SwissFEL (SFEL)
------------------------------------------------------------------------------
@@ -137,8 +137,8 @@ begin
o_mgt_status(16) <= sl_rx0_slide;
o_mgt_status(17) <= sl_gtxe_rx_sync_done;
o_mgt_status(19 downto 18) <= o_mgt.rx.RXNOTINTABLE(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(21 downto 20) <= o_mgt.rx.RXDISPERR(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(31 downto 22) <= B"00_0000_0000"; -- undefined
o_mgt_status(23 downto 20) <= o_mgt.rx.RXDISPERR(3 downto 0); -- Byte 1 + Byte 0
o_mgt_status(31 downto 24) <= B"0000_0000"; -- undefined
-- GTXE RX IF ---------------------------------------------------------------------

6
sim/config.tcl
View File

@@ -33,8 +33,10 @@ add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
psi_common_pulse_cc.vhd \
psi_common_async_fifo.vhd \
psi_common_clk_meas.vhd \
psi_common_pulse_shaper.vhd \
psi_common_delay.vhd \
psi_common_pulse_shaper_cfg.vhd \
psi_common_delay_cfg.vhd \
psi_common_simple_cc.vhd \
psi_common_status_cc.vhd \
} -tag psi_common
# EVR320 Decoder

3
tb/evr320_decoder_tb.vhd
View File

@@ -174,7 +174,7 @@ begin
evr320_data_filter_inst: entity work.evr320_data_filter
generic map (
ADDRESS => FILTER_ADDRESS,
SWAP => false
NUM_BYTES => 8
)
port map (
@@ -182,6 +182,7 @@ begin
i_stream_data => dec_stream_data,
i_stream_addr => dec_stream_addr,
i_stream_valid => dec_stream_valid,
i_address => FILTER_ADDRESS,
o_data => filter_data,
o_valid => filter_valid
);

912
tb/evr320_ifc1210_wrapper_tb.vhd
View File

@@ -21,459 +21,573 @@ context uvvm_util.uvvm_util_context;
-- Work library (application) --------------------------------------------------
library work;
use work.evr320_pkg.all;
use work.psi_common_math_pkg.all;
entity evr320_ifc1210_wrapper_tb is
end entity;
architecture testbench of evr320_ifc1210_wrapper_tb is
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
constant C_RXUSRCLK_CYCLE : time := 7 ns;
constant C_USRCLK_CYCLE : time := 8 ns;
constant C_EVT_NR : integer := 4;
constant C_MEM_DATA_WIDTH : integer := 32; -- 32|64 (64 bit used for tosca2 on ifc1210)
constant C_EVENT_RECORDER : boolean := true;
constant C_EVENT_REC_FLAGS : std_logic_vector(11 downto 6) := B"1101_11";
constant g_EVENT_NR_SOS : integer range 0 to 255 := 16#20#;
constant g_EVENT_NR_0 : integer range 0 to 255 := 16#00#;
constant g_EVENT_NR_1 : integer range 0 to 255 := 16#04#;
constant g_EVENT_NR_2 : integer range 0 to 255 := 16#00#;
constant g_EVENT_NR_3 : integer range 0 to 255 := 16#00#;
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
constant C_RXUSRCLK_CYCLE : time := 7 ns;
constant C_USRCLK_CYCLE : time := 8 ns;
constant C_EVT_NR : integer := 4;
constant C_MEM_DATA_WIDTH : integer := 32; -- 32|64 (64 bit used for tosca2 on ifc1210)
constant C_EVENT_RECORDER : boolean := true;
constant C_EVENT_REC_FLAGS : std_logic_vector(11 downto 6) := B"1101_11";
constant g_EVENT_NR_SOS : integer range 0 to 255 := 16#20#;
constant g_EVENT_NR_0 : integer range 0 to 255 := 16#00#;
constant g_EVENT_NR_1 : integer range 0 to 255 := 16#04#;
constant g_EVENT_NR_2 : integer range 0 to 255 := 16#00#;
constant g_EVENT_NR_3 : integer range 0 to 255 := 16#00#;
---------------------------------------------------------------------------
-- MGT stream
---------------------------------------------------------------------------
type mgt_stream_sample_type is record
data : std_logic_vector(7 downto 0);
data_k : std_logic_vector(0 downto 0);
event : std_logic_vector(7 downto 0);
event_k : std_logic_vector(0 downto 0);
end record mgt_stream_sample_type;
---------------------------------------------------------------------------
-- MGT stream
---------------------------------------------------------------------------
type mgt_stream_sample_type is record
data : std_logic_vector(7 downto 0);
data_k : std_logic_vector(0 downto 0);
event : std_logic_vector(7 downto 0);
event_k : std_logic_vector(0 downto 0);
end record mgt_stream_sample_type;
type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
signal mgt_stream_index : integer range 0 to 511 := 0;
signal mgt_stream : mgt_stream_type(511 downto 0) := (others => (others => (others => '0')));
signal mgt_stream_index : integer range 0 to 511 := 0;
signal mgt_stream : mgt_stream_type(511 downto 0) := (others => (others => (others => '0')));
-----------------------------------------------------------------------------
-- Timing decoder interface
-----------------------------------------------------------------------------
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Timing decoder interface
-----------------------------------------------------------------------------
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
-- Decoder stream
type dec_stream_type is record
data : std_logic_vector(7 downto 0);
addr : std_logic_vector(10 downto 0);
end record dec_stream_type;
type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
-- Decoder stream
type dec_stream_type is record
data : std_logic_vector(7 downto 0);
addr : std_logic_vector(10 downto 0);
end record dec_stream_type;
type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
signal dec_stream_valid : std_logic;
signal dec_stream_check : dec_stream_check_arr(0 to 2047);
signal dec_stream_recv_bytes : integer range 0 to 2047;
signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
signal dec_stream_valid : std_logic;
signal dec_stream_check : dec_stream_check_arr(0 to 2047);
signal dec_stream_recv_bytes : integer range 0 to 2047;
type segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
signal segment_addr : std_logic_vector(7 downto 0);
signal segment_data : segment_data_arr(0 to 2047);
signal segment_length : natural range 0 to 2047;
type segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
signal segment_addr : std_logic_vector(7 downto 0);
signal segment_data : segment_data_arr(0 to 2047);
signal segment_length : natural range 0 to 2047;
constant FILTER_ADDRESS : std_logic_vector(11 downto 0) := x"028";
constant FILTER_NUM_BYTES : integer := 8;
constant STIMULI_RUNS : integer := 2;
constant FILTER_ADDRESS : std_logic_vector(11 downto 0) := x"028";
constant FILTER_NUM_BYTES : integer := 8;
constant STIMULI_RUNS : integer := 2;
signal filter_data, filter_data_check : std_logic_vector(63 downto 0) := (others => '0');
signal filter_valid : std_logic := '0';
signal filter_data, filter_data_check : std_logic_vector(63 downto 0) := (others => '0');
signal filter_valid : std_logic := '0';
signal tmem_i : tmem_bus_in_t;
signal tmem_o : tmem_bus_out_t;
signal tmem_clk : std_logic;
signal tmem_rst : std_logic;
signal tmem_data_rd : std_logic_vector(63 downto 0);
signal tmem_i : tmem_bus_in_t;
signal tmem_o : tmem_bus_out_t;
signal tmem_clk : std_logic;
signal tmem_rst : std_logic;
signal tmem_data_rd : std_logic_vector(63 downto 0);
signal tick1sec : std_logic;
signal tick1sec : std_logic;
alias rxlos is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rst : std_logic>>;
alias clk_evr is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.clk_evr : std_logic>>;
alias rxdata is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_data : std_logic_vector(15 downto 0)>>;
alias rxcharisk is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_charisk : std_logic_vector(1 downto 0)>>;
alias sos_event is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_sos_event : std_logic>>;
alias usr_events is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_usr_events : std_logic_vector(3 downto 0)>>;
alias evr_stable is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.evr_stable : std_logic>>;
alias rxlos is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rst : std_logic>>;
alias clk_evr is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.clk_evr : std_logic>>;
alias rxdata is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_data : std_logic_vector(15 downto 0)>>;
alias rxcharisk is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_charisk : std_logic_vector(1 downto 0)>>;
alias sos_event is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_sos_event : std_logic>>;
alias usr_events is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_usr_events : std_logic_vector(3 downto 0)>>;
alias evr_stable is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.evr_stable : std_logic>>;
--*** stimuli for delay & pulse width ***
signal usr_event_width_sti : typ_arr_width := (to_uslv(2, log2ceil(MaxDuration_c)), --sos set to 2
to_uslv(3, log2ceil(MaxDuration_c)), --0
to_uslv(4, log2ceil(MaxDuration_c)), --1
to_uslv(5, log2ceil(MaxDuration_c)), --2
to_uslv(6, log2ceil(MaxDuration_c)) --3
);
signal usr_event_delay_sti : typ_arr_delay := (to_uslv(2, log2ceil(MaxDelay_c)), --sos set to 2
to_uslv(3, log2ceil(MaxDelay_c)), --0
to_uslv(4, log2ceil(MaxDelay_c)), --1
to_uslv(5, log2ceil(MaxDelay_c)), --2
to_uslv(6, log2ceil(MaxDelay_c)) --3
);
begin
tmem_o.TMEM_BUSY_o <= '0';
tmem_o.TMEM_PIPE_o <= "10";
tmem_o.TMEM_BUSY_o <= '0';
tmem_o.TMEM_PIPE_o <= "10";
-----------------------------------------------------------------------------
-- Timing decoder
-----------------------------------------------------------------------------
evr320_ifc1210_wrapper_inst : entity work.evr320_ifc1210_wrapper
generic map(
g_EVT_DURATION => (1, 1, 1, 1, 1),
g_EVT_HOLDOFF => (0, 0, 0, 0, 0),
g_EVT_DELAY => (1, 1, 1, 1, 1),
g_MGT_LOCATION => "GTXE1_X0Y16", -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY => "SFEL", -- "HIPA" | "SFEL"
g_EVENT_RECORDER => C_EVENT_RECORDER, -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ => 125000000 -- Xuser Clk Frequency in Hz
)
port map(
tick1sec_i => tick1sec,
--------------------------------------------------------------------------
-- Debug interface
--------------------------------------------------------------------------
debug_clk => open,
debug => open,
--------------------------------------------------------------------------
-- TOSCA2 TMEM interface
--------------------------------------------------------------------------
xuser_CLK => tmem_clk,
xuser_RESET => tmem_rst,
xuser_TMEM_ENA => tmem_i.TMEM_ENA_i,
xuser_TMEM_WE => tmem_i.TMEM_WE_i,
xuser_TMEM_ADD => tmem_i.TMEM_ADD_i(13 downto 3),
xuser_TMEM_DATW => tmem_i.TMEM_DATW_i,
xuser_TMEM_DATR => tmem_o.TMEM_DATR_o,
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i => '0',
mgt_sfp_los_i => '0',
mgt_rx_n => '0',
mgt_rx_p => '0',
mgt_tx_n => open,
mgt_tx_p => open,
mgt_status_o => open,
mgt_control_i => (others => '0'),
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o => open,
usr_events_o => open,
sos_event_o => open,
usr_events_adj_o => open,
sos_events_adj_o => open,
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i => '1',
stream_data_o => open,
stream_addr_o => open,
stream_valid_o => open
);
-----------------------------------------------------------------------------
-- Timing decoder
-----------------------------------------------------------------------------
evr320_ifc1210_wrapper_inst : entity work.evr320_ifc1210_wrapper
generic map(
g_MGT_LOCATION => "GTXE1_X0Y16", -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY => "SFEL", -- "HIPA" | "SFEL"
g_EVENT_RECORDER => C_EVENT_RECORDER, -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ => 125000000 -- Xuser Clk Frequency in Hz
)
port map(
--------------------------------------------------------------------------
-- Debug interface
--------------------------------------------------------------------------
debug_clk => open,
debug => open,
--------------------------------------------------------------------------
-- TOSCA2 TMEM interface
--------------------------------------------------------------------------
xuser_CLK => tmem_clk,
xuser_RESET => tmem_rst,
xuser_TMEM_ENA => tmem_i.TMEM_ENA_i,
xuser_TMEM_WE => tmem_i.TMEM_WE_i,
xuser_TMEM_ADD => tmem_i.TMEM_ADD_i(13 downto 3),
xuser_TMEM_DATW => tmem_i.TMEM_DATW_i,
xuser_TMEM_DATR => tmem_o.TMEM_DATR_o,
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i => '0',
mgt_sfp_los_i => '0',
mgt_rx_n => '0',
mgt_rx_p => '0',
mgt_tx_n => open,
mgt_tx_p => open,
mgt_status_o => open,
mgt_control_i => (others => '0'),
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o => open,
usr_events_o => open,
sos_event_o => open,
usr_events_adj_o => open,
sos_events_adj_o => open,
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i => '1',
stream_data_o => open,
stream_addr_o => open,
stream_valid_o => open
);
gen_pulse(tick1sec, '1', usr_clk, 1, "");
-----------------------------------------------------------------------------
-- MGT / User clock
-----------------------------------------------------------------------------
clock_generator(usr_clk, C_USRCLK_CYCLE);
tmem_clk <= usr_clk;
gen_pulse(tick1sec, '1', usr_clk, 1, "");
-----------------------------------------------------------------------------
-- MGT / User clock
-----------------------------------------------------------------------------
clock_generator(usr_clk, C_USRCLK_CYCLE);
tmem_clk <= usr_clk;
-- Simulate MGT Clock
mgt_clk_proc : process
begin
clk_evr <= force in '0';
loop
wait for C_RXUSRCLK_CYCLE / 2;
clk_evr <= force in not (clk_evr);
end loop;
end process;
-- Simulate MGT Clock
mgt_clk_proc : process
begin
clk_evr <= force in '0';
loop
wait for C_RXUSRCLK_CYCLE / 2;
clk_evr <= force in not (clk_evr);
end loop;
end process;
-----------------------------------------------------------------------------
-- Decoder reset due to MGT main status
-----------------------------------------------------------------------------
process
begin
rxlos <= force in '1';
tmem_rst <= '1';
wait for 50 ns;
wait until (falling_edge(clk_evr));
rxlos <= force in '0';
tmem_rst <= '0';
wait;
end process;
-----------------------------------------------------------------------------
-- Decoder reset due to MGT main status
-----------------------------------------------------------------------------
process
begin
rxlos <= force in '1';
tmem_rst <= '1';
wait for 50 ns;
wait until (falling_edge(clk_evr));
rxlos <= force in '0';
tmem_rst <= '0';
wait;
end process;
-----------------------------------------------------------------------------
-- Read stimuli file
-----------------------------------------------------------------------------
file_blk : block
file file_stimuli : text;
type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done);
begin
process
variable file_line : line;
variable data, event : std_logic_vector(7 downto 0);
variable data_k, event_k : std_logic_vector(0 downto 0);
variable space : character;
variable i : integer;
variable parse_fsm : parse_fsm_state := idle;
variable payload_cnt : integer range 0 to 2047;
variable event_cnt_total : integer := 0;
variable event_cnt_0 : integer := 0;
variable event_cnt_1 : integer := 0;
variable event_cnt_2 : integer := 0;
variable event_cnt_3 : integer := 0;
variable event_cnt_user : integer := 0;
begin
file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode);
readline(file_stimuli, file_line); -- comment
readline(file_stimuli, file_line); -- comment
i := 0;
-- read line by line from .dat file:
while not endfile(file_stimuli) loop
readline(file_stimuli, file_line);
hread(file_line, event);
read(file_line, event_k);
read(file_line, space);
read(file_line, space);
hread(file_line, data);
read(file_line, space);
read(file_line, data_k);
-- write to array:
mgt_stream(i).data <= data;
mgt_stream(i).data_k <= data_k;
mgt_stream(i).event <= event;
mgt_stream(i).event_k <= event_k;
mgt_stream_index <= i;
--debug output:
--log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) & " event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX)
-- & " data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & " ");
-----------------------------------------------------------------------------
-- Read stimuli file
-----------------------------------------------------------------------------
file_blk : block
file file_stimuli : text;
type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done);
begin
process
variable file_line : line;
variable data, event : std_logic_vector(7 downto 0);
variable data_k, event_k : std_logic_vector(0 downto 0);
variable space : character;
variable i : integer;
variable parse_fsm : parse_fsm_state := idle;
variable payload_cnt : integer range 0 to 2047;
variable event_cnt_total : integer := 0;
variable event_cnt_0 : integer := 0;
variable event_cnt_1 : integer := 0;
variable event_cnt_2 : integer := 0;
variable event_cnt_3 : integer := 0;
variable event_cnt_user : integer := 0;
begin
file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode);
readline(file_stimuli, file_line); -- comment
readline(file_stimuli, file_line); -- comment
i := 0;
-- read line by line from .dat file:
while not endfile(file_stimuli) loop
readline(file_stimuli, file_line);
hread(file_line, event);
read(file_line, event_k);
read(file_line, space);
read(file_line, space);
hread(file_line, data);
read(file_line, space);
read(file_line, data_k);
-- write to array:
mgt_stream(i).data <= data;
mgt_stream(i).data_k <= data_k;
mgt_stream(i).event <= event;
mgt_stream(i).event_k <= event_k;
mgt_stream_index <= i;
--debug output:
--log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) & " event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX)
-- & " data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & " ");
-- Parse only segment:
----------------------
case (parse_fsm) is
when idle =>
if (data = x"5C" and data_k = "1") then -- check if frame start
parse_fsm := seg_start;
end if;
when seg_start =>
parse_fsm := seg_addr;
when seg_addr =>
segment_addr <= data;
parse_fsm := seg_wait;
when seg_wait =>
parse_fsm := seg_payload;
payload_cnt := 0;
when seg_payload =>
if (data = x"3C" and data_k = "1") then -- check if frame end
parse_fsm := seg_done;
else
segment_data(payload_cnt) <= data;
parse_fsm := seg_payload_wait;
segment_length <= payload_cnt + 1;
end if;
when seg_payload_wait =>
payload_cnt := payload_cnt + 1;
parse_fsm := seg_payload;
when seg_done =>
-- done
end case;
i := i + 1;
end loop;
file_close(file_stimuli);
wait;
end process;
end block;
-- Parse only segment:
----------------------
case (parse_fsm) is
when idle =>
if (data = x"5C" and data_k = "1") then -- check if frame start
parse_fsm := seg_start;
end if;
when seg_start =>
parse_fsm := seg_addr;
when seg_addr =>
segment_addr <= data;
parse_fsm := seg_wait;
when seg_wait =>
parse_fsm := seg_payload;
payload_cnt := 0;
when seg_payload =>
if (data = x"3C" and data_k = "1") then -- check if frame end
parse_fsm := seg_done;
else
segment_data(payload_cnt) <= data;
parse_fsm := seg_payload_wait;
segment_length <= payload_cnt + 1;
end if;
when seg_payload_wait =>
payload_cnt := payload_cnt + 1;
parse_fsm := seg_payload;
when seg_done =>
-- done
end case;
i := i + 1;
end loop;
file_close(file_stimuli);
wait;
end process;
end block;
---------------------------------------------------------
-- Wait for Start of Sequence Event
---------------------------------------------------------
process
begin
wait until rising_edge(sos_event);
log(ID_CTRL, "Start of Sequence Event Received: " & to_string(std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)), HEX, AS_IS, INCL_RADIX)); -- change to await_value
end process;
---------------------------------------------------------
-- Wait for Start of Sequence Event
---------------------------------------------------------
process
begin
wait until rising_edge(sos_event);
log(ID_CTRL, "Start of Sequence Event Received: " & to_string(std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)), HEX, AS_IS, INCL_RADIX)); -- change to await_value
end process;
--------------------------------------------------------------------------
-- Stimuli MGT
--------------------------------------------------------------------------
process
begin
wait until rising_edge(clk_evr);
for b in 0 to STIMULI_RUNS - 1 loop
log(ID_LOG_HDR, "Send stimuli stream to MGT - RUN " & to_string(b + 1));
for idx in 0 to mgt_stream_index loop
--log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX));
wait until rising_edge(clk_evr);
rxdata <= force out mgt_stream(idx).data & mgt_stream(idx).event;
rxcharisk <= force out mgt_stream(idx).data_k & mgt_stream(idx).event_k;
end loop;
wait for 3 us;
end loop;
wait;
end process;
--------------------------------------------------------------------------
-- Stimuli MGT
--------------------------------------------------------------------------
process
begin
wait until rising_edge(clk_evr);
for b in 0 to STIMULI_RUNS - 1 loop
log(ID_LOG_HDR, "Send stimuli stream to MGT - RUN " & to_string(b + 1));
for idx in 0 to mgt_stream_index loop
--log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX));
wait until rising_edge(clk_evr);
rxdata <= force out mgt_stream(idx).data & mgt_stream(idx).event;
rxcharisk <= force out mgt_stream(idx).data_k & mgt_stream(idx).event_k;
end loop;
wait for 3 us;
end loop;
wait;
end process;
-----------------------------------------------------------------------------
-- Main Process
-----------------------------------------------------------------------------
process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant c_TB_NAME : string := "evr320_decoder_tb";
variable latency_cnt_val : unsigned(31 downto 0);
-----------------------------------------------------------------------------
-- Main Process
-----------------------------------------------------------------------------
process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant c_TB_NAME : string := "evr320_decoder_tb";
variable latency_cnt_val : unsigned(31 downto 0);
begin
disable_log_msg(ID_GEN_PULSE);
--------------------------------------------------------------------------
log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE);
--------------------------------------------------------------------------
begin
disable_log_msg(ID_GEN_PULSE);
--------------------------------------------------------------------------
log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE);
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Get out of reset, enable events
--------------------------------------------------------------------------
evr_params.event_enable(0) <= '0' when g_EVENT_NR_0 = 0 else '1';
evr_params.event_enable(1) <= '0' when g_EVENT_NR_1 = 0 else '1';
evr_params.event_enable(2) <= '0' when g_EVENT_NR_2 = 0 else '1';
evr_params.event_enable(3) <= '0' when g_EVENT_NR_3 = 0 else '1';
evr_params.event_numbers(0) <= std_logic_vector(to_unsigned(g_EVENT_NR_0, 8));
evr_params.event_numbers(1) <= std_logic_vector(to_unsigned(g_EVENT_NR_1, 8));
evr_params.event_numbers(2) <= std_logic_vector(to_unsigned(g_EVENT_NR_2, 8));
evr_params.event_numbers(3) <= std_logic_vector(to_unsigned(g_EVENT_NR_3, 8));
evr_params.cs_min_cnt <= X"00000000";
evr_params.cs_min_time <= X"00000000";
mem_addr <= x"000";
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
--------------------------------------------------------------------------
-- Get out of reset, enable events
--------------------------------------------------------------------------
evr_params.event_enable(0) <= '0' when g_EVENT_NR_0 = 0 else '1';
evr_params.event_enable(1) <= '0' when g_EVENT_NR_1 = 0 else '1';
evr_params.event_enable(2) <= '0' when g_EVENT_NR_2 = 0 else '1';
evr_params.event_enable(3) <= '0' when g_EVENT_NR_3 = 0 else '1';
evr_params.event_numbers(0) <= std_logic_vector(to_unsigned(g_EVENT_NR_0, 8));
evr_params.event_numbers(1) <= std_logic_vector(to_unsigned(g_EVENT_NR_1, 8));
evr_params.event_numbers(2) <= std_logic_vector(to_unsigned(g_EVENT_NR_2, 8));
evr_params.event_numbers(3) <= std_logic_vector(to_unsigned(g_EVENT_NR_3, 8));
evr_params.cs_min_cnt <= X"00000000";
evr_params.cs_min_time <= X"00000000";
mem_addr <= x"000";
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
-- overwrite evr_stable flag:
evr_stable <= force '1';
-- overwrite evr_stable flag:
evr_stable <= force '1';
-- enable sos event and set event number:
TMEM_BUS_WRITE(seqid => "A00_001",
tmem_add => x"00_0040",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_2001",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
-- enable sos event and set event number:
TMEM_BUS_WRITE(seqid => "A00_001",
tmem_add => x"00_0040",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_2001",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
wait for 20 ns;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_001",
tmem_add => x"00_0040",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_001",
tmem_add => x"00_0040",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
wait for 20 ns;
-- ---------------------------------------------------------
-- send delay and width parameters:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0050",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0005_0004_0003_0002",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
check_value(tmem_data_rd, x"0000_0000_0000_2001", ERROR, "TMEM Write/Read check: EVR SOS Event Cfg");
wait for 20 ns;
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_0020",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0050",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
wait for 20 ns;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
check_value(tmem_data_rd, x"0005_0004_0003_0002", ERROR, "TMEM Write/Read check: EVR Puls delay Event Cfg");
-- ---------------------------------------------------------
-- ---------------------------------------------------------
-- send width and width parameters:
TMEM_BUS_WRITE(seqid => "A00_003",
tmem_add => x"00_0058",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0009_0008_0007_0006",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
wait for 20 ns;
check_value(tmem_data_rd, x"0000_0000_0000_0020", ERROR, "TMEM Write/Read check: lat. meas. event nr");
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_003",
tmem_add => x"00_0058",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
-- 1. check latency measurement counter:
----------------------------------------
await_value(sos_event, '1', 0 ns, 2 us, ERROR, "wait for sos event");
wait for 2000 ns;
latency_cnt_val := x"00000000";
wait for 20 ns;
-- read latency measurement counter without rearm:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(63 downto 32));
check_value(tmem_data_rd, x"0009_0008_0007_0006", ERROR, "TMEM Write/Read check: EVR Puls Width Event Cfg");
-- ---------------------------------------------------------
-- ---------------------------------------------------------
-- send width and width parameters for SOS:
TMEM_BUS_WRITE(seqid => "A00_004",
tmem_add => x"00_0060",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0001_0001",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"000000F5", x"000000FE", ERROR, "Latency Counter Value (no-rearm) Check after 2us");
wait for 20 ns;
-- 2. read latency measurement counter again with rearm:
--------------------------------------------------------
latency_cnt_val := x"00000000";
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_004",
tmem_add => x"00_0060",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
wait for 20 ns;
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"000000FA", x"00000102", ERROR, "Latency Counter Value (rearm) Check directly after first read");
check_value(tmem_data_rd, x"0000_0000_0001_0001", ERROR, "TMEM Write/Read check: SOS width & delay Event Cfg");
-- ---------------------------------------------------------
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_0020",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
-- read 2. time rearm latency counter which should be cleared now:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
check_value(latency_cnt_val, x"00000000", ERROR, "Check if counter is cleared");
wait for 20 ns;
-- 4. read latency measurement counter with rearm:
--------------------------------------------------
await_value(sos_event, '1', 0 ns, 3 us, ERROR, "wait for sos event");
wait for 1 us;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
-- read counter and rearm:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"0000007A", x"00000080", ERROR, "Latency Counter Value (rearm) Check after 1us");
wait for 20 ns;
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_0020",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
--------------------------------------------------------------------------
-- Test Done
--------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
-- ------------------------------------------------------------------------
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- ------------------------------------------------------------------------
-- assert error if UVVM mismatch flag is 1 => upstream info for scripts/jenkins
assert shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse = 0 report "###ERROR### - UVVM Mismatch Errors with Expected Errors -> Check Log for details" severity ERROR;
std.env.stop(0);
wait; -- stop simulation
wait for 20 ns;
end process;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0000_0000_0000_0020", ERROR, "TMEM Write/Read check: lat. meas. event nr");
-- 1. check latency measurement counter:
----------------------------------------
await_value(sos_event, '1', 0 ns, 2 us, ERROR, "wait for sos event");
wait for 2000 ns;
latency_cnt_val := x"00000000";
-- read latency measurement counter without rearm:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(63 downto 32));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"000000F5", x"000000FE", ERROR, "Latency Counter Value (no-rearm) Check after 2us");
-- 2. read latency measurement counter again with rearm:
--------------------------------------------------------
latency_cnt_val := x"00000000";
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"000000FA", x"00000102", ERROR, "Latency Counter Value (rearm) Check directly after first read");
-- read 2. time rearm latency counter which should be cleared now:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
check_value(latency_cnt_val, x"00000000", ERROR, "Check if counter is cleared");
-- 4. read latency measurement counter with rearm:
--------------------------------------------------
await_value(sos_event, '1', 0 ns, 3 us, ERROR, "wait for sos event");
wait for 1 us;
-- read counter and rearm:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0038",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
check_value_in_range(latency_cnt_val, x"0000007A", x"00000080", ERROR, "Latency Counter Value (rearm) Check after 1us");
--------------------------------------------------------------------------
-- Test Done
--------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
-- ------------------------------------------------------------------------
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- ------------------------------------------------------------------------
-- assert error if UVVM mismatch flag is 1 => upstream info for scripts/jenkins
assert shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse = 0 report "###ERROR### - UVVM Mismatch Errors with Expected Errors -> Check Log for details" severity ERROR;
std.env.stop(0);
wait; -- stop simulation
end process;
end architecture testbench;