EVR STABLE: add generic to discard for hipa this statement EVR STABLE

hdl/evr320_decoder.vhd

@@ -24,8 +24,10 @@ use work.evr320_pkg.all;
 entity evr320_decoder is
    generic
    (
+      FACILITY                    : string  := "SFEL";      -- "HIPA" | "SFEL"
       EVENT_RECORDER              : boolean := false;
-      MEM_DATA_WIDTH              : integer := 32
+      MEM_DATA_WIDTH              : integer := 32;
+      EXP_REC_CLK_FREQ            : natural := 142_800_000  -- in Hz 
    );
    port
    (
@@ -73,6 +75,7 @@ architecture behavioral of evr320_decoder is
    -----------------------------------------------------------------------------
    -- Constant
    -----------------------------------------------------------------------------
+   --
    constant HIGH                  : std_logic := '1';
    constant LOW                   : std_logic := '0';
    constant LOW_slv               : std_logic_vector(15 downto  0) := (others => '0');
@@ -180,7 +183,6 @@ architecture behavioral of evr320_decoder is
    signal   mem_data_wren               : std_logic := '0';
    signal   mem_data_wr_addr            : std_logic_vector(10 downto  0) := (others => '0');
    signal   mem_data_wr_byte            : std_logic_vector( 7 downto  0) := (others => '0');
-   signal   mem_data                    : std_logic_vector(11+8-1 downto 0);
    -- Data memory read      
    signal   mem_data_dpram              : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
    signal   mem_data_event0             : std_logic_vector(MEM_DATA_WIDTH - 1 downto  0) := (others => '0');
@@ -222,7 +224,9 @@ architecture behavioral of evr320_decoder is
 --   attribute fsm_safe_state : string;
 --   attribute fsm_safe_state of frame_fsm      : signal is "default_state";
 --   attribute fsm_safe_state of mem_fsm        : signal is "default_state";
-
+  
+   constant evr_stable_time_int_c : natural := EXP_REC_CLK_FREQ/100;
+   constant evr_stable_time_slv_c : std_logic_vector(cs_timeout_cnt'range):= std_logic_vector(to_unsigned(evr_stable_time_int_c, cs_timeout_cnt'length));
 begin
 
    -----------------------------------------------------------------------------
@@ -231,9 +235,10 @@ begin
    debug_clk                      <= i_mgt_rx_clk;
    debug( 15 downto   0)          <= i_mgt_rx_data;
    debug( 17 downto  16)          <= i_mgt_rx_charisk;
-   debug( 23 downto  18)          <= (others=>'0');
-   debug( 31 downto  24)          <= (others => '0');
-   debug( 35 downto  32)          <= "0001" when (frame_fsm = frame_idle    ) else
+   debug(18)                      <= evr_stable;--new
+   debug(26 downto 19)            <= i_evr_params.event_numbers(1);
+   debug(34 downto 27)            <= i_evr_params.event_numbers(2);
+   debug(38 downto  35)          <= "0001" when (frame_fsm = frame_idle    ) else
                                      "0010" when (frame_fsm = frame_addr_gap) else
                                      "0011" when (frame_fsm = frame_addr    ) else
                                      "0100" when (frame_fsm = frame_data_gap) else
@@ -243,7 +248,7 @@ begin
                                      "1000" when (frame_fsm = frame_chk2_gap) else
                                      "1001" when (frame_fsm = frame_chk2    ) else
                                      "0000";
-   debug( 39 downto  36)          <= (others => '0');
+   debug( 39)                     <=  '0';
    debug( 40)                     <= usr_events( 0)( 3);
    debug( 41)                     <= usr_events( 1)( 3);
    debug( 42)                     <= usr_events( 2)( 3);
@@ -268,7 +273,7 @@ begin
    end generate dbg_evt_rec;
 
    dbg_no_evt_rec: if not(EVENT_RECORDER) generate
-      debug(127 downto  64)       <= (others => '0');
+      
    end generate dbg_no_evt_rec;
    
 
@@ -290,6 +295,7 @@ begin
    
    -----------------------------------------------------------------------------
    -- evr stable state
+   -- TODO: Perform the sync according to k28.5
    -----------------------------------------------------------------------------
    prc_evr_stable : process(i_mgt_rx_clk)
    begin
@@ -297,9 +303,9 @@ begin
          if (i_mgt_rst = '1') then
             evr_stable            <= '0';
          else
-            if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and 
-                (std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and 
-                (std_logic_vector(cs_timeout_cnt) < X"15CA20")) then
+            if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt)    and 
+                (std_logic_vector(cs_min_time) > i_evr_params.cs_min_time)  and 
+                (std_logic_vector(cs_timeout_cnt) < evr_stable_time_slv_c)) then -- make generics depending on recovery_clock
                evr_stable      <= '1';
             else
                evr_stable      <= '0';
@@ -318,13 +324,21 @@ begin
          if (i_mgt_rst = '1') then
             usr_events            <= (others => (others => '0'));
          else
-            for i in 0 to 3 loop
-               if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto  0) = i_evr_params.event_numbers(i)) and (evr_stable = '1')) then
+           for i in 0 to 3 loop
+           if FACILITY = "HIPA" then
+              if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto  0) = i_evr_params.event_numbers(i))) then
                   usr_events(i)   <= "1111";
                else
                   usr_events(i)   <= usr_events(i)( 2 downto  0) & '0';
                end if;
-            end loop;
+          else
+            if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto  0) = i_evr_params.event_numbers(i))and (evr_stable = '1')) then
+                  usr_events(i)   <= "1111";
+               else
+                  usr_events(i)   <= usr_events(i)( 2 downto  0) & '0';
+               end if;
+           end if;
+           end loop;
          end if;
       end if;
    end process;
@@ -710,9 +724,6 @@ begin
    mem_data_wr_addr               <= frame_data_rd_addr;
    mem_data_wr_byte               <= frame_data_rd_byte;
 
-   -- concatenate - this avoids an internal error in ghdl v0.37!
-   mem_data                       <= mem_data_wr_addr & mem_data_wr_byte;
-
    -----------------------------------------------------------------------------
    -- Address delay for read data mux
    -----------------------------------------------------------------------------
@@ -874,7 +885,7 @@ begin
       OutRst  => '0',
       
       -- Input Data
-      InData  => mem_data,
+      InData  => mem_data_wr_addr & mem_data_wr_byte,
       InVld   => mem_data_wren,
       InRdy   => open,
       

hdl/evr320_ifc1210_wrapper.vhd

@@ -53,6 +53,9 @@ entity evr320_ifc1210_wrapper is
     mgt_tx_p         : out std_logic;   -- MGT TX P
     mgt_status_o     : out std_logic_vector(31 downto 0); -- MGT Status
     mgt_control_i    : in  std_logic_vector(31 downto 0); -- MGT Control      
+    mgt_rx_data_o    : out std_logic_Vector(15 downto 0); -- for debug purpose
+    mgt_rx_charisk_o : out std_logic_vector(1 downto 0);  -- for debug purpose
+    
     ---------------------------------------------------------------------------
     -- User interface MGT clock
     ---------------------------------------------------------------------------
@@ -104,10 +107,8 @@ architecture rtl of evr320_ifc1210_wrapper is
   signal event_recorder_control       : typ_evt_rec_ctrl;
   signal event_recorder_control_sync  : typ_evt_rec_ctrl;
   signal event_recorder_control_xuser : typ_evt_rec_ctrl;
-  signal evr_latency_measure_A_stat   : typ_rec_latency_measure_stat;
-  signal evr_latency_measure_A_ctrl   : typ_rec_latency_measure_ctrl;
-  signal evr_latency_measure_B_stat   : typ_rec_latency_measure_stat;
-  signal evr_latency_measure_B_ctrl   : typ_rec_latency_measure_ctrl;
+  signal evr_latency_measure_stat     : typ_rec_latency_measure_stat;
+  signal evr_latency_measure_ctrl     : typ_rec_latency_measure_ctrl;
   signal evr_frequency                : std_logic_vector(31 downto 0) := (others => '0');
   signal debug_data                   : std_logic_vector(127 downto 0);
   signal decoder_event_valid          : std_logic;
@@ -165,8 +166,10 @@ begin
   -- --------------------------------------------------------------------------
   evr320_decoder_inst : entity work.evr320_decoder
     generic map(
-      EVENT_RECORDER => g_EVENT_RECORDER,
-      MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH)
+      FACILITY          => g_FACILITY,
+      EVENT_RECORDER    => g_EVENT_RECORDER,
+      MEM_DATA_WIDTH    => c_TOSCA2_DATA_WIDTH,
+      EXP_REC_CLK_FREQ  => 50_632_820)
     port map(
       -- Debug interface
       debug_clk             => debug_clk,
@@ -221,7 +224,8 @@ begin
       o_mgt_rx_data    => mgt_rx_data,
       o_mgt_rx_charisk => mgt_rx_charisk
     );
-
+   mgt_rx_charisk_o <= mgt_rx_charisk;
+   mgt_rx_data_o    <= mgt_rx_data;
   -- --------------------------------------------------------------------------
   -- TMEM 
   -- -------------------------------------------------------------------------- 
@@ -241,10 +245,8 @@ begin
       evr_frequency_i            => evr_frequency,
       evr_evt_rec_status_i       => event_recorder_status,
       evr_evt_rec_control_o      => event_recorder_control_xuser,
-      evr_latency_measure_A_stat_i => evr_latency_measure_A_stat,
-      evr_latency_measure_A_ctrl_o => evr_latency_measure_A_ctrl,
-      evr_latency_measure_B_stat_i => evr_latency_measure_B_stat,
-      evr_latency_measure_B_ctrl_o => evr_latency_measure_B_ctrl,
+      evr_latency_measure_stat_i => evr_latency_measure_stat,
+      evr_latency_measure_ctrl_o => evr_latency_measure_ctrl,
       mgt_status_i               => mgt_status,
       mgt_reset_o                => mgt_reset_tmem_evr,
       mem_clk_o                  => mem_clk,
@@ -272,63 +274,83 @@ begin
     );
 
   -- --------------------------------------------------------------------------
-  -- Latency Measurement for IFC1210 Interrupts
+  -- Event Latency Measurement for SW tests
   -- --------------------------------------------------------------------------
-  latency_meas_A_inst : entity work.latency_measurement
-    generic map(
-      CLK_FREQ_HZ  => g_XUSER_CLK_FREQ
-    )
-    port map(
-    evr_clk_i             => clk_evr,
-    xuser_clk_i           => xuser_CLK,
-    decoder_event_valid_i => decoder_event_valid,
-    decoder_event_i       => decoder_event,
-    status_o              => evr_latency_measure_A_stat,
-    ctrl_i                => evr_latency_measure_A_ctrl
-    );
+  lat_meas_block : block
+    type state_type is (armed, count);
+    signal state                   : state_type;
+    signal counter                 : unsigned(31 downto 0);
+    signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
+    signal event_detected          : std_logic_vector(3 downto 0);
+    signal event_detected_sync     : std_logic_vector(1 downto 0);
+    constant MAX_COUNT             : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 10, 32); -- MAX 100ms ~ 10Hz
+  begin
 
-  latency_meas_B_inst : entity work.latency_measurement
-    generic map(
-      CLK_FREQ_HZ  => g_XUSER_CLK_FREQ
-    )
-    port map(
-    evr_clk_i             => clk_evr,
-    xuser_clk_i           => xuser_CLK,
-    decoder_event_valid_i => decoder_event_valid,
-    decoder_event_i       => decoder_event,
-    status_o              => evr_latency_measure_B_stat,
-    ctrl_i                => evr_latency_measure_B_ctrl
-    );
+    -- Process: filter events for matching event_nr register:
+    ---------------------------------------------------------
+    ext_event_proc : process(clk_evr)
+    begin
+      if (rising_edge(clk_evr)) then
+        -- sync to MGT clock domain:
+        event_nr_sync <= evr_latency_measure_ctrl.event_nr;
+        event_nr      <= event_nr_sync;
+
+        -- check if event has been detected and stretch pulse: 
+        event_detected <= event_detected(2 downto 0) & '0';
+        if (decoder_event_valid = '1' and decoder_event = event_nr) then
+          event_detected <= (others => '1');
+        end if;
+      end if;
+    end process;
+
+    -- Process: Counter when configured event has been detected:
+    ------------------------------------------------------------
+    lat_meas_proc : process(xuser_CLK, counter)
+    begin
+      if rising_edge(xuser_CLK) then
+        -- sync to user clock domain:
+        event_detected_sync <= event_detected_sync(0) & event_detected(3);
+
+        -- counter FSM:
+        ---------------
+        case state is
+          -- counter is armed:
+          when armed =>
+            counter <= (others => '0');
+            -- start counting when event detected (rising edge):
+            if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
+              state <= count;
+            end if;
+
+          -- counting:
+          when count =>
+            -- count only up to 10ms, and stop:
+            if (counter < MAX_COUNT) then
+              counter <= counter + 1;
+            end if;
+            if (evr_latency_measure_ctrl.counter_arm = '1') then
+              state <= armed;
+            end if;
+        end case;
+      end if;
+
+      evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
+    end process;
+
+  end block;
 
   -- --------------------------------------------------------------------------
   -- Add delay output
   -- --------------------------------------------------------------------------
   output_delay_block : block
-    signal rst0_s, rst1_s      : std_logic; -- double stage sync for reset
+    --signal rst0_s, rst1_s      : std_logic; -- double stage sync for reset
     signal usr_evt_shaped_s    : std_logic_vector(4 downto 0);
     signal usr_events_adj_s    : std_logic_vector(4 downto 0);
     signal usr_events_concat_s : std_logic_vector(4 downto 0);
-    signal mmcm_locked         : std_logic;
-    signal rxpll_locked        : std_logic;
-    signal evr_rst_in          : std_logic;
 
   begin
-
-    rxpll_locked <= mgt_status(1);
-    mmcm_locked  <= mgt_status(2);
-    evr_rst_in   <= xuser_RESET or (not rxpll_locked) or (not mmcm_locked);
-
-    --*** double stage sync for reset ***--
-    proc_rst : process(clk_evr)
-    begin
-      if rising_edge(clk_evr) then
-        rst0_s <= evr_rst_in;
-        rst1_s <= rst0_s;
-      end if;
-    end process;
-
-    evr_rst_s <= rst1_s;
-
+    
+    evr_rst_s           <= mgt_status(15); -- RXLOSSOFSYNC
     usr_events_concat_s <= usr_events_s & sos_event_s;
 
     gene_adj_out : for i in 0 to 4 generate
@@ -341,7 +363,7 @@ begin
                     MaxDuration_g => MaxDuration_c,
                     RstPol_g      => '1')
         port map(clk_i   => clk_evr,
-                 rst_i   => rst1_s,
+                 rst_i   => evr_rst_s,
                  width_i => usr_event_width_s(i),
                  hold_i  => (others => '0'),
                  dat_i   => usr_events_concat_s(i),
@@ -355,7 +377,7 @@ begin
                     RamBehavior_g   => "RBW",
                     Hold_g          => True)
         port map( clk_i => clk_evr,
-                  rst_i => rst1_s,
+                  rst_i => evr_rst_s,
                   dat_i(0) => usr_evt_shaped_s(i),
                   str_i => '1',
                   del_i => usr_event_delay_s(i),

hdl/evr320_pkg.vhd

@@ -12,7 +12,6 @@
 --------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
 use work.psi_common_math_pkg.all;
 
 package evr320_pkg is
@@ -20,9 +19,9 @@ package evr320_pkg is
   -- --------------------------------------------------------------------------
   -- Constants                                                    
   -- --------------------------------------------------------------------------
-  constant c_CHECKSUM_MIN_EVT       : std_logic_vector(31 downto 0)   := X"00000064"; -- Check sum min count for events 100
-  constant c_CHECKSUM_MIN_TIME      : std_logic_vector(31 downto 0)   := X"0015CA20"; -- Check sum min time for events 10 ms
-  constant c_SOS_EVENT_DEFAULT      : std_logic_vector( 7 downto 0)   := X"26";       -- default start-of-sequence (SOS) event
+  constant c_CHECKSUM_MIN_EVT     : std_logic_vector(31 downto 0)   := X"00000064"; -- Check sum min count for events 100
+  constant c_CHECKSUM_MIN_TIME    : std_logic_vector(31 downto 0)   := X"0015CA20"; -- Check sum min time for events 10 ms
+  constant c_SOS_EVENT_DEFAULT    : std_logic_vector( 7 downto 0)   := X"20";       -- decimal 32
   
  
   -- --------------------------------------------------------------------------
@@ -61,17 +60,14 @@ package evr320_pkg is
 
   type typ_rec_latency_measure_stat is record
     counter_val          : std_logic_vector(31 downto 0);
-    event_detected       : std_logic;
   end record;
   
   --*** Type record and constant for new feature pulse width & delay ***
-  constant MaxDuration_c          : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles 
-  constant MaxDelay_c             : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles 
-  constant UsrEventWidthDefault_c : std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0) := std_logic_vector(to_unsigned(4, log2ceil(MaxDuration_c)));  -- default pulse width of usr_events_adj_o
+  constant MaxDuration_c  : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles 
+  constant MaxDelay_c     : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles 
   type typ_arr_width is array (4 downto 0) of std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0);
   type typ_arr_delay is array (4 downto 0) of std_logic_vector(log2ceil(MaxDelay_c)-1 downto 0);
   
-  
   -- --------------------------------------------------------------------------
   -- Type Initialisation                                                      
   -- --------------------------------------------------------------------------
@@ -86,8 +82,7 @@ package evr320_pkg is
 
   constant c_INIT_REC_LATENCY_MEASURE_CTRL : typ_rec_latency_measure_ctrl :=  (event_nr    => (others =>'0'),
                                                                                counter_arm => '1'); 
-  constant c_INIT_REC_LATENCY_MEASURE_STAT : typ_rec_latency_measure_stat :=  (counter_val => (others =>'0'),
-                                                                                event_detected => '0');
+  constant c_INIT_REC_LATENCY_MEASURE_STAT : typ_rec_latency_measure_stat :=  (counter_val => (others =>'0'));
   -- --------------------------------------------------------------------------
   -- Function Prototypes
   -- --------------------------------------------------------------------------

hdl/evr320_tmem.vhd

@@ -37,11 +37,9 @@ entity evr320_tmem is
     evr_frequency_i               : in    std_logic_vector(31 downto  0);
     evr_evt_rec_status_i          : in    typ_evt_rec_status;           
     evr_evt_rec_control_o         : out   typ_evt_rec_ctrl;           
-    evr_latency_measure_A_stat_i  : in    typ_rec_latency_measure_stat;
-    evr_latency_measure_A_ctrl_o  : out   typ_rec_latency_measure_ctrl;
-    evr_latency_measure_B_stat_i  : in    typ_rec_latency_measure_stat;
-    evr_latency_measure_B_ctrl_o  : out   typ_rec_latency_measure_ctrl;
-    mgt_status_i                  : in    std_logic_vector(31 downto  0) := (others=>'0');
+    evr_latency_measure_stat_i    : in    typ_rec_latency_measure_stat;
+    evr_latency_measure_ctrl_o    : out   typ_rec_latency_measure_ctrl;
+    mgt_status_i                  : in    std_logic_vector(31 downto  0);          
     mgt_reset_o                   : out   std_logic;          
     mem_clk_o                     : out   std_logic; 
     mem_addr_o                    : out   std_logic_vector(10 downto  0); 
@@ -104,15 +102,18 @@ architecture rtl of evr320_tmem is
   signal er_control_concat      : std_logic_vector(31 downto 0)   := (others => '0');
 
   -- latency measurement
-  signal lat_A_counter_arm, lat_B_counter_arm           : std_logic                       := '0'; 
-  signal lat_A_event_nr, lat_B_event_nr                 : std_logic_vector(7 downto 0)    := c_SOS_EVENT_DEFAULT;
-  signal lat_A_event_detected, lat_B_event_detected     : std_logic_vector(7 downto 0);
-  signal lat_A_arm, lat_B_arm                           : std_logic := '0';
-  signal lat_A_arm_edge, lat_B_arm_edge                 : std_logic_vector(1 downto 0)    := (others=>'0');
+  signal lat_counter_arm        : std_logic                       := '0'; 
+  signal lat_event_nr           : std_logic_vector(7 downto 0)    := x"26";  -- default SOS event
+  signal lat_counter_val        : std_logic_vector(31 downto 0)   := (others=>'0'); 
 
+  -- signal evr_force              : std_logic_vector(3 downto 0)    := (others => '0');
+  -- signal evr_force_rd           : std_logic_vector(3 downto 0)    := (others => '0');  -- readback
+  -- signal evr_force_pulse        : typ_arr4(3 downto 0)            := (others => (others => '0'));
+  
   -- event pulse config
-  signal evr_puls_width_cfg_s : typ_arr_width := (others => UsrEventWidthDefault_c);
-  signal evr_puls_delay_cfg_s : typ_arr_delay := (others => (others => '0'));
+  
+  signal evr_puls_width_cfg_s : typ_arr_width :=((others=>(others=>'0')));
+  signal evr_puls_delay_cfg_s : typ_arr_delay :=((others=>(others=>'0')));
 
 -- ----------------------------------------------------------------------------
 -- ----------------------------------------------------------------------------
@@ -127,36 +128,10 @@ begin
   event_numbers_concat  <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0);
   er_handshake_status   <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid);
   er_control_concat     <= X"0000" & er_event_number & bit2byte(er_event_enable);
-
-  -- -----------------------------
-  -- latency measurement, arm 
-  -- -----------------------------
-  process (xuser_CLK)
-  begin
-    if rising_edge(xuser_CLK) then
-      -- edge detection of latency arm:
-      lat_A_arm_edge <= lat_A_arm_edge(0) & lat_A_arm;
-      lat_A_counter_arm <= lat_A_arm_edge(0) and not lat_A_arm_edge(1);
-      lat_B_arm_edge <= lat_B_arm_edge(0) & lat_B_arm;
-      lat_B_counter_arm <= lat_B_arm_edge(0) and not lat_B_arm_edge(1);
-
-      if (evr_latency_measure_A_stat_i.event_detected = '1') then
-        lat_A_event_detected  <= (others=>'1');
-      end if;
-      if (lat_A_counter_arm = '1') then
-        lat_A_event_detected  <= (others=>'0');
-      end if;
-
-      if (evr_latency_measure_B_stat_i.event_detected = '1') then
-        lat_B_event_detected  <= (others=>'1');
-      end if;
-      if (lat_B_counter_arm = '1') then
-        lat_B_event_detected  <= (others=>'0');
-      end if;
-    end if;
-  end process;
+  lat_counter_val       <= evr_latency_measure_stat_i.counter_val;
   
   -- --------------------------------------------------------------------------
+  -- TODO: proper CDC
   -- Synchronisation to xuser_CLK                                                      
   -- --------------------------------------------------------------------------
   prc_sync_xuser: process (xuser_CLK)
@@ -183,24 +158,21 @@ begin
   -- --------------------------------------------------------------------------
   -- Read operation                                                       
   -- --------------------------------------------------------------------------
-  blk_tmemrd : block
-
-  begin
   read_tmem_evr: process(xuser_CLK)
   begin
     if (rising_edge(xuser_CLK)) then
+      lat_counter_arm <= '0';
       if (xuser_TMEM_ENA_reg = '1') then
         if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
           case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
             when X"0" =>    xuser_TMEM_DATR <=  event_numbers_concat       & X"0000" & mgt_status_evr;           -- 64bit / ByteAddr 000
             when X"1" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & X"0000_00" & bit2byte(mgt_reset);   -- 64bit / ByteAddr 008   --> 0x00C = not implemented in ifc1210
-            when X"2" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & bit2byte(event_enable);             -- 64bit / ByteAddr 010   --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ...
+            when X"2" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & bit2byte(event_enable);             -- 64bit / ByteAddr 010   --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ...  evr_force
             when X"3" =>    xuser_TMEM_DATR <=  evr_frequency              & reserved(31 downto 0);              -- 64bit / ByteAddr 018   --> 0x018 = Implementation Options + c_EVR_Location_vec 
             when X"4" =>    xuser_TMEM_DATR <=  cs_min_time                & cs_min_cnt;                         -- 64bit / ByteAddr 020
             when X"5" =>    xuser_TMEM_DATR <=  reserved(63 downto 0);                                           -- 64bit / ByteAddr 028
-            when X"6" =>    xuser_TMEM_DATR <=  evr_latency_measure_A_stat_i.counter_val   & 
-                                                lat_B_event_detected & lat_A_event_detected & lat_B_event_nr & lat_A_event_nr;               -- 64bit / ByteAddr 030
-            when X"7" =>    xuser_TMEM_DATR <=  evr_latency_measure_B_stat_i.counter_val   & reserved(31 downto 0);              -- 64bit / ByteAddr 038
+            when X"6" =>    xuser_TMEM_DATR <=  lat_counter_val            & X"000000" & lat_event_nr;           -- 64bit / ByteAddr 030
+            when X"7" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
             when X"8" =>    xuser_TMEM_DATR <=  er_handshake_status        & er_control_concat;                  -- 64bit / ByteAddr 040                
             when X"9" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)     & er_status.usr_events_counter;       -- 64bit / ByteAddr 048   
             when X"A" =>    xuser_TMEM_DATR <=  evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050   
@@ -215,7 +187,6 @@ begin
     end if;
   end process;
 
-  end block;
   
   -- --------------------------------------------------------------------------
   -- Write operation  - Byte control                                           
@@ -227,8 +198,6 @@ begin
       -- default assignments
       er_data_ack   <= er_data_ack(2 downto 0) & '0';
       er_error_ack  <= er_error_ack(2 downto 0) & '0';
-      lat_A_arm <= '0';
-      lat_B_arm <= '0';
 
       
       if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
@@ -278,21 +247,8 @@ begin
         end if;
         -----------------------------------------------------------------------------------------------------------------
         if xuser_TMEM_ADD_reg(6 downto 3) = X"6" then --ByteAddr 030   Latency Measurement
-          if xuser_TMEM_WE_reg(0) = '1' then lat_A_event_nr ( 7 downto  0)  <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
-          if xuser_TMEM_WE_reg(1) = '1' then lat_B_event_nr ( 7 downto  0)  <= xuser_TMEM_DATW_reg(15 downto  8); end if; 
-       -- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8)       <= xuser_TMEM_DATW_reg(15 downto 8); end if;
-       -- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16)      <= xuser_TMEM_DATW_reg(23 downto 16); end if;
-       -- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24)      <= xuser_TMEM_DATW_reg(31 downto 24); end if;
-       -- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto  0)      <= xuser_TMEM_DATW_reg(39 downto 32); end if;
-       -- if xuser_TMEM_WE_reg(5) = '1' then -reserved- (15 downto  8)      <= xuser_TMEM_DATW_reg(47 downto 40); end if;
-       -- if xuser_TMEM_WE_reg(6) = '1' then -reserved- (23 downto 16)      <= xuser_TMEM_DATW_reg(55 downto 48); end if;
-       -- if xuser_TMEM_WE_reg(7) = '1' then -reserved- (31 downto 24)      <= xuser_TMEM_DATW_reg(63 downto 56); end if;
-        end if;
-        -----------------------------------------------------------------------------------------------------------------
-        if xuser_TMEM_ADD_reg(6 downto 3) = X"7" then --ByteAddr 038   Latency Measurement
-          if xuser_TMEM_WE_reg(0) = '1' then lat_A_arm                      <= xuser_TMEM_DATW_reg(0); end if;
-          if xuser_TMEM_WE_reg(1) = '1' then lat_B_arm                      <= xuser_TMEM_DATW_reg(8); end if;
-       -- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8)       <= xuser_TMEM_DATW_reg(15 downto 8); end if;
+          if xuser_TMEM_WE_reg(0) = '1' then lat_event_nr ( 7 downto  0)    <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
+       -- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto  8)      <= xuser_TMEM_DATW_reg(15 downto  8); end if;
        -- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16)      <= xuser_TMEM_DATW_reg(23 downto 16); end if;
        -- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24)      <= xuser_TMEM_DATW_reg(31 downto 24); end if;
        -- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto  0)      <= xuser_TMEM_DATW_reg(39 downto 32); end if;
@@ -340,11 +296,9 @@ begin
   -- --------------------------------------------------------------------------
   mem_clk_o                   <= xuser_CLK;
   mem_addr_o                  <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
-  evr_params_o                <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
+  --event recorder had to be also added to cdc
   evr_evt_rec_control_o       <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
   mgt_reset_o                 <= mgt_reset;
-  evr_latency_measure_A_ctrl_o  <= (lat_A_event_nr, lat_A_counter_arm);
-  evr_latency_measure_B_ctrl_o  <= (lat_B_event_nr, lat_B_counter_arm);
 
   -- --------------------------------------------------------------------------
   -- add CDC output
@@ -393,6 +347,57 @@ begin
     evr_pulse_width_o(3) <= output_s(143 downto 128);
     evr_pulse_width_o(4) <= output_s(159 downto 144);
   end block;
+  
+  block_cdc_evr_code_param : block
+    signal input_s, output_s : std_logic_vector(108 downto 0);
+  begin
+    -- ------------------------------------------------------------------------
+    -- Assemble Input
+    -- ------------------------------------------------------------------------
+    --** event  numbers **
+    input_s( 7 downto 0)     <= event_numbers(0);
+    input_s(15 downto 8)     <= event_numbers(1);
+    input_s(23 downto 16)    <= event_numbers(2);
+    input_s(31 downto 24)    <= event_numbers(3);
+    --** event pulse enable **
+    input_s(35 downto 32)    <= event_enable;
+    --** time counter **
+    input_s(67 downto 36)    <= cs_min_time;
+    input_s(99 downto 68)    <= cs_min_cnt;
+    --** latency counter **
+    input_s(100)             <= lat_counter_arm;
+    input_s(108 downto 101)  <= lat_event_nr;
+
+    -- Instance
+    inst_cdc_fast_stat : entity work.psi_common_status_cc
+      generic map(DataWidth_g => input_s'length)
+      port map(ClkA   => xuser_CLK,
+              RstInA  => xuser_RESET,
+              RstOutA => open,
+              DataA   => input_s,
+              ClkB    => evr_clk_i,
+              RstInB  => evr_rst_i,
+              RstOutB => open,
+              DataB   => output_s);
+    -- ------------------------------------------------------------------------
+    -- Disassemble Output
+    -- ------------------------------------------------------------------------
+    --** event  numbers **
+    evr_params_o.event_numbers(0) <=  output_s( 7 downto 0) ;  
+    evr_params_o.event_numbers(1) <=  output_s(15 downto 8) ;  
+    evr_params_o.event_numbers(2) <=  output_s(23 downto 16);  
+    evr_params_o.event_numbers(3) <=  output_s(31 downto 24);  
+    --** event pulse enable **                         
+    evr_params_o.event_enable     <=  output_s(35 downto 32);
+    --** time counter **
+    evr_params_o.cs_min_time      <=  output_s(67 downto 36); 
+    evr_params_o.cs_min_cnt       <=  output_s(99 downto 68);  
+    --** latency counter **
+    evr_latency_measure_ctrl_o.counter_arm  <= output_s(100)            ;
+    evr_latency_measure_ctrl_o.event_nr     <= output_s(108 downto 101) ;
+  end block;                                                            
 
 end rtl;
-
+-- ----------------------------------------------------------------------------
+-- ////////////////////////////////////////////////////////////////////////////
+-- ----------------------------------------------------------------------------

hdl/latency_measurement.vhd

@@ -1,98 +0,0 @@
- ---------------------------------------------------------------------------
---                       Paul Scherrer Institute (PSI)
--- ---------------------------------------------------------------------------
--- Unit    : latency_measurement.vhd
--- Author  : Jonas Purtschert
--- ---------------------------------------------------------------------------
--- Copyright© PSI, Section DSV
--- ---------------------------------------------------------------------------
--- Comment : Latency Measurement for IFC1210 Interrupt latency debugging
--- ---------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.math_real.all;
-
-use work.evr320_pkg.all;
-
-entity latency_measurement is
-  generic (
-    CLK_FREQ_HZ : natural := 125000000 -- Xuser Clk Frequency in Hz
-  );
-  port (
-    evr_clk_i             : in std_logic;
-    xuser_clk_i           : in std_logic;
-    decoder_event_valid_i : in std_logic;
-    decoder_event_i       : in std_logic_vector(7 downto 0);
-    status_o              : out typ_rec_latency_measure_stat;
-    ctrl_i                : in typ_rec_latency_measure_ctrl
-  );
-end latency_measurement;
-
-architecture rtl of latency_measurement is
-
-  -- --------------------------------------------------------------------------
-  -- Signal, Types, Constants
-  -- --------------------------------------------------------------------------
-    type state_type is (armed, count);
-    signal state                   : state_type;
-    signal counter                 : unsigned(31 downto 0);
-    signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
-    signal event_detected          : std_logic_vector(3 downto 0);
-    signal event_detected_sync     : std_logic_vector(1 downto 0);
-    constant MAX_COUNT             : unsigned(31 downto 0) := to_unsigned(CLK_FREQ_HZ / 100, 32); -- MAX 10ms
-
-begin
-
-    -- Process: filter events for matching event_nr register:
-    ---------------------------------------------------------
-    ext_event_proc : process(evr_clk_i)
-    begin
-      if (rising_edge(evr_clk_i)) then
-        -- sync to MGT clock domain:
-        event_nr_sync <= ctrl_i.event_nr;
-        event_nr      <= event_nr_sync;
-
-        -- check if event has been detected and stretch pulse: 
-        event_detected <= event_detected(2 downto 0) & '0';
-        if (decoder_event_valid_i = '1' and decoder_event_i = event_nr) then
-          event_detected <= (others => '1');
-        end if;
-      end if;
-    end process;
-
-    -- Process: Counter when configured event has been detected:
-    ------------------------------------------------------------
-    lat_meas_proc : process(xuser_clk_i, counter)
-    begin
-      if rising_edge(xuser_clk_i) then
-        -- sync to user clock domain:
-        event_detected_sync <= event_detected_sync(0) & event_detected(3);
-
-        -- counter FSM:
-        ---------------
-        case state is
-          -- counter is armed:
-          when armed =>
-            counter <= (others => '0');
-            -- start counting when event detected (rising edge):
-            if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
-              state <= count;
-            end if;
-
-          -- counting:
-          when count =>
-            -- count only up to 10ms, and stop:
-            if (counter < MAX_COUNT) then
-              counter <= counter + 1;
-            end if;
-            if (ctrl_i.counter_arm = '1') then
-              state <= armed;
-            end if;
-        end case;
-      end if;
-      status_o.counter_val <= std_logic_vector(counter);
-      status_o.event_detected <= event_detected_sync(event_detected_sync'left);
-    end process;
-
-end rtl;

hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd

@@ -7,7 +7,7 @@
 --         : Patric Bucher, Section DSV
 -- Version : $Revision: 1.1 $
 ------------------------------------------------------------------------------
--- Copyright© PSI, Section Diagnostic
+-- Copyright<EFBFBD> PSI, Section Diagnostic
 ------------------------------------------------------------------------------
 -- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz
 ------------------------------------------------------------------------------
@@ -384,7 +384,7 @@ begin
       RXPLLLKDET                      =>      o_mgt.ctrl.RXPLLLKDET ,                         --RXPLLLKDET_OUT,
       RXPLLLKDETEN                    =>      '1',                                            --
       RXPLLPOWERDOWN                  =>      '0',                                            --
-      RXPLLREFSELDY                   =>      "000",                                          -- GREFCLKRX
+      RXPLLREFSELDY                   =>      "000",                                          --GREFCLKRX
       RXRATE                          =>      "00",                                           --
       RXRATEDONE                      =>      open,                                           --
       RXRESETDONE                     =>      o_mgt.ctrl.RXRESETDONE ,                        --RXRESETDONE_OUT,

hdl/v6vlx_gtxe1_wrapper.vhd

@@ -7,7 +7,7 @@
 --         : Patric Bucher, Section DSV
 -- Version : $Revision: 1.1 $
 ------------------------------------------------------------------------------
--- Copyright© PSI, Section Diagnostic
+-- Copyright<EFBFBD> PSI, Section Diagnostic
 ------------------------------------------------------------------------------
 -- Comment : Wrapper vor Virtex-6 GTX ready to use in HIPA and SwissFEL (SFEL)
 ------------------------------------------------------------------------------
@@ -137,8 +137,8 @@ begin
   o_mgt_status(16)             <= sl_rx0_slide;
   o_mgt_status(17)             <= sl_gtxe_rx_sync_done;
   o_mgt_status(19 downto 18)   <= o_mgt.rx.RXNOTINTABLE(1 downto 0);  -- Byte 1 + Byte 0
-  o_mgt_status(21 downto 20)   <= o_mgt.rx.RXDISPERR(1 downto 0);     -- Byte 1 + Byte 0
-  o_mgt_status(31 downto 22)   <= B"00_0000_0000";                    -- undefined
+  o_mgt_status(23 downto 20)   <= o_mgt.rx.RXDISPERR(3 downto 0);     -- Byte 1 + Byte 0
+  o_mgt_status(31 downto 24)   <= B"0000_0000";                    -- undefined
   
 
   -- GTXE RX IF ---------------------------------------------------------------------
@@ -260,7 +260,7 @@ begin
       else
         case s_align_fsm is
           when align_idle =>
-            if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' or o_mgt.rx.RXBYTEISALIGNED = '0' then
+            if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' then
               s_align_fsm   <= align_slide;
             end if;
           when align_slide =>

sim/config.tcl

@@ -64,6 +64,7 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
 # EVR320 Decoder Testbench
 add_sources $LibPath/Firmware/VHDL/evr320/tb {
 	evr320_decoder_tb.vhd \
+	evr320_ifc1210_wrapper_tb.vhd \
 } -tag evr320_tb
 
 # EVR320 IFC1210 Wrapper Testbench

tb/evr320_decoder_tb.vhd

@@ -80,7 +80,7 @@ architecture testbench of evr320_decoder_tb is
   signal   usr_clk               : std_logic := '0';
   signal   evr_params            : typ_evr320_params;
   signal   mem_addr              : std_logic_vector(11 downto  0) := (others => '0');
-  signal   mem_data              : std_logic_vector(C_MEM_DATA_WIDTH-1 downto  0) := (others => '0');
+  signal   mem_data              : std_logic_vector(31 downto  0) := (others => '0');
   
   -- Decoder stream
   type dec_stream_type is record
@@ -169,14 +169,12 @@ begin
      --------------------------------------------------------------------------
      o_usr_events                => usr_events,
      o_usr_events_ext            => open,
-     o_sos_event                 => sos_event,
-     o_event                     => open,
-     o_event_valid               => open
+     o_sos_event                 => sos_event
   );
 
   evr320_data_filter_inst: entity work.evr320_data_filter
   generic map (
-    SWAP      => true, -- non-swapped uses LE layout; our check below converts to BE
+    SWAP      => false 
     NUM_BYTES => 8
   )
   port map (
@@ -401,7 +399,7 @@ begin
     variable i : integer := 0;
     type state is (idle, payload, frame_end, segment_nr);
     variable mem_base : integer range 0 to 127;
-    variable segment_data_word : std_logic_vector(C_MEM_DATA_WIDTH-1 downto 0);
+    variable segment_data_word : std_logic_vector(31 downto 0);
     variable var_filter_offset : integer range 0 to 2047;
     variable var_filter_word : std_logic_vector(FILTER_NUM_BYTES*8-1 downto 0);
     variable expected_evt_rec_events : integer range 0 to 255 := 0;
@@ -488,51 +486,37 @@ begin
         log(ID_DATA, "Check expected Event Flags after SOS Event detected");
         ----------------------------------------------------------------------
         wait until rising_edge(usr_clk);
-        if (C_MEM_DATA_WIDTH = 32) then
-          for addr in 0 to 63 loop    
-            mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
-            wait_num_rising_edge_plus_margin(usr_clk, 1, 1 ns);
+        for addr in 0 to 63 loop    
+          mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
+          wait until rising_edge(usr_clk);
+          await_value(mem_data(0),  all_expected_events(4*addr),     0 ns, 1 ns, ERROR, "Event " & to_string(4*addr)     & " Flag");
+          await_value(mem_data(8),  all_expected_events(4*addr + 1), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 1) & " Flag");
+          await_value(mem_data(16), all_expected_events(4*addr + 2), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 2) & " Flag");
+          await_value(mem_data(24), all_expected_events(4*addr + 3), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 3) & " Flag");
+        end loop;
+        
+        ----------------------------------------------------------------------
+        log(ID_DATA, "Check Memory block border");
+        ----------------------------------------------------------------------
+        -- read data mux switching made visible with delayed address.
+        mem_addr <= C_EVENT_REC_FLAGS & "000000";
+        wait until rising_edge(usr_clk);
+        wait for C_USRCLK_CYCLE/4;
+        for addr in 62 to 65 loop    
+          mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
+          wait until rising_edge(usr_clk);
+          check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
+          wait for C_USRCLK_CYCLE/4;
+          if (addr < 64) then
             check_value(mem_data(0),  all_expected_events(4*addr),     ERROR, "Event " & to_string(4*addr)     & " Flag");
             check_value(mem_data(8),  all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
             check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
             check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
-            wait until rising_edge(usr_clk);
-          end loop;
-        elsif (C_MEM_DATA_WIDTH = 64) then
-          for addr in 0 to 31 loop    
-            mem_addr <= '0' & C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 5));
-            wait_num_rising_edge_plus_margin(usr_clk, 1, 1 ns);
-            for j in 0 to C_MEM_DATA_WIDTH/8 loop
-              check_value(mem_data(8*j),  all_expected_events(8*addr + j),     ERROR, "Event " & to_string(8*addr + j)     & " Flag");
-            end loop;
-          end loop;
-        else
-          error("Unsupported width of C_MEM_DATA_WIDTH");
-        end if;
+          else
+            check_value(mem_data,  X"0000_0000", ERROR, "After Event Recorder Mem Map");
+          end if;
+        end loop;
         
-        -- ----------------------------------------------------------------------
-        -- log(ID_DATA, "Check Memory block border");
-        -- ----------------------------------------------------------------------
-        if (C_MEM_DATA_WIDTH = 32) then
-          -- read data mux switching made visible with delayed address.
-          mem_addr <= C_EVENT_REC_FLAGS & "000000";
-          wait until rising_edge(usr_clk);
-          wait for C_USRCLK_CYCLE/4;
-          for addr in 62 to 65 loop    
-            mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
-            wait until rising_edge(usr_clk);
-            check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
-            wait for C_USRCLK_CYCLE/4;
-            if (addr < 64) then
-              check_value(mem_data(0),  all_expected_events(4*addr),     ERROR, "Event " & to_string(4*addr)     & " Flag");
-              check_value(mem_data(8),  all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
-              check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
-              check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
-            else
-              check_value(mem_data,  X"0000_0000", ERROR, "After Event Recorder Mem Map");
-            end if;
-          end loop;
-        end if;
         ----------------------------------------------------------------------
         log(ID_DATA, "Check expected Event Recorder User Events");
         ----------------------------------------------------------------------
@@ -544,24 +528,22 @@ begin
     --------------------------------------------------------------------------
     log(ID_LOG_HDR, "Read DPRAM buffer", C_SCOPE);
     --------------------------------------------------------------------------
-    if (C_MEM_DATA_WIDTH = 32) then
-      wait for 50 * C_USRCLK_CYCLE;
-      log(ID_DATA, "Read Segment from DPRAM");
-      -- print 16 words from dpram data buffer:
-      for offset in 0 to segment_length/4-1 loop
-        mem_base := to_integer(unsigned(segment_addr));
-        mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
-        wait until rising_edge(usr_clk);
-        wait until rising_edge(usr_clk);
-        wait until rising_edge(usr_clk);
-        segment_data_word := segment_data(offset*4+3) 
-                              & segment_data(offset*4+2) 
-                              & segment_data(offset*4+1) 
-                              & segment_data(offset*4);
-        check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment");
-        --log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX));
-      end loop;
-    end if;
+    wait for 50 * C_USRCLK_CYCLE;
+    log(ID_DATA, "Read Segment from DPRAM");
+    -- print 16 words from dpram data buffer:
+    for offset in 0 to segment_length/4-1 loop
+      mem_base := to_integer(unsigned(segment_addr));
+      mem_addr <= std_logic_vector(to_unsigned(4*mem_base + offset , 12));
+      wait until rising_edge(usr_clk);
+      wait until rising_edge(usr_clk);
+      wait until rising_edge(usr_clk);
+      segment_data_word := segment_data(offset*4+3) 
+                            & segment_data(offset*4+2) 
+                            & segment_data(offset*4+1) 
+                            & segment_data(offset*4);
+      check_value(mem_data, segment_data_word, ERROR, "Compare DPRAM with Sent Segment");
+      --log(ID_PACKET_DATA, "Data buffer DPRAM: addr=0x" & to_string(mem_addr, HEX) & " data=0x" & to_string(mem_data, HEX));
+    end loop;
 
     --------------------------------------------------------------------------
     -- Test Done

tb/stimuli_mgt.dat

@@ -167,7 +167,7 @@ FE 0  00 0   event 254
 FF 0  00 0   event 255
 BC 1  00 0   align
 00 0  00 0   gap
-00 0  00 0   gap
+0F 0  00 0   gap
 00 0  00 0   gap
 BC 1  00 0   align
 00 0  00 0   gap