Jungfraujoch

add_multipixel_tb.cpp

FPGA: Add multipixel - handle division by 2 and 4 for multipixels.

2023-10-24 18:05:48 +02:00

add_multipixel.cpp

FPGA: Add multipixel - handle division by 2 and 4 for multipixels.

2023-10-24 18:05:48 +02:00

adu_histo.cpp

FPGA: Fix ADU histogram for high summation

2023-11-17 13:04:12 +01:00

arp.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

axis_broadcast.cpp

FPGA: spot_finder added

2023-09-26 18:54:31 +02:00

axis_helpers.cpp

FPGA: rename axis_256_to_512.cpp file

2023-10-21 15:38:40 +02:00

CMakeLists.txt

FPGA: data analysis is done based on 24-bit numbers - allowing frame summation

2023-10-28 16:35:33 +02:00

data_collection_fsm.cpp

FPGA: Increase max summation to 256

2023-11-16 21:32:37 +01:00

datamover_model.h

parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS)

2023-10-18 12:10:00 +02:00

ethernet.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

frame_generator.cpp

FPGA: Max module number is 32

2023-11-01 15:55:06 +01:00

frame_summation_reorder_compl_tb.cpp

HLS: Added frame_summation core

2023-10-26 22:31:09 +02:00

frame_summation_reorder_compl.cpp

FPGA: Increase max summation to 256

2023-11-16 21:32:37 +01:00

frame_summation_tb.cpp

FPGA: data analysis is done based on 24-bit numbers - allowing frame summation

2023-10-28 16:35:33 +02:00

frame_summation.cpp

FPGA: Clean-up unnecessary comment

2023-11-17 13:04:29 +01:00

hls_bitshuffle.cpp

HLS: Changes to allow cosimulation with Vitis HLS

2023-10-18 14:44:30 +02:00

hls_jfjoch.h

FPGA: Increase max summation to 256

2023-11-16 21:32:37 +01:00

host_writer.cpp

FPGA: Fix problems in summation and related cores

2023-11-02 20:25:29 +01:00

icmp.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

integration.cpp

FPGA: data analysis is done based on 24-bit numbers - allowing frame summation

2023-10-28 16:35:33 +02:00

ip_header_checksum.h

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

ipv4.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

jf_conversion.cpp

FPGA: Increase data width of conversion to 18-bit. This allows to use full unsigned precision + raw data are handled properly.

2023-11-07 19:11:37 +01:00

load_calibration.cpp

FPGA: frame_generator and load_calibration return value for error checking

2023-11-01 13:31:41 +01:00

load_from_hbm.cpp

FPGA: Max module number is 32

2023-11-01 15:55:06 +01:00

mask_missing.cpp

FPGA: Fix license

2023-09-21 13:10:55 +02:00

module_upside_down_tb.cpp

FPGA: Add option to invert modules upside down

2023-10-25 22:20:45 +02:00

module_upside_down.cpp

FPGA: Add option to invert modules upside down

2023-10-25 22:20:45 +02:00

parallel_stream.h

parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS)

2023-10-18 12:10:00 +02:00

save_to_hbm.cpp

FPGA: Max module number is 32

2023-11-01 15:55:06 +01:00

sls_detector.cpp

FPGA: sls_detector had hardcoded max module number -> fixed

2023-11-01 13:28:17 +01:00

spot_finder_tb.cpp

FPGA: data analysis is done based on 24-bit numbers - allowing frame summation

2023-10-28 16:35:33 +02:00

spot_finder.cpp

FPGA: data analysis is done based on 24-bit numbers - allowing frame summation

2023-10-28 16:35:33 +02:00

stream_24bit_conv_tb.cpp

FPGA: data analysis is done based on 24-bit numbers - allowing frame summation

2023-10-28 16:35:33 +02:00

stream_24bit_conv.cpp

Fix tests + re-run FPGA synthesis

2023-11-07 21:42:16 +01:00

stream_merge.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

timer.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00

udp.cpp

Remove open source license (for now)

2023-09-15 10:47:21 +02:00