FPGA: Fix ADU histogram for high summation

fpga/hls/adu_histo.cpp

@@ -14,7 +14,7 @@ void adu_histo(STREAM_512 &data_in,
 #pragma HLS INTERFACE register both axis port=m_axis_completion
 #pragma HLS INTERFACE register both axis port=s_axis_completion
 
-    ap_uint<19> count[64][ADU_HISTO_BIN_COUNT]; // log2(16*512*1024/64) = 17
+    ap_uint<24> count[64][ADU_HISTO_BIN_COUNT]; // log2(256*512*1024/64) = 23
 #pragma HLS BIND_STORAGE variable=count type=ram_t2p impl=bram
 #pragma HLS ARRAY_PARTITION variable=count type=complete dim=1
 
@@ -29,7 +29,7 @@ void adu_histo(STREAM_512 &data_in,
 
     packet_512_t packet_in;
     data_in >> packet_in;
-    ap_uint<7> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..127
+    ap_uint<8> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..255
     data_out << packet_in;
 
     axis_completion cmpl;