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b2abb0f92b
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v1.0.0-rc.94
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2025-10-25 22:05:47 +02:00 |
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0b480f762c
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v1.0.0-rc.93
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2025-10-23 15:48:46 +02:00 |
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c44a07aac2
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v1.0.0-rc.90
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2025-10-02 15:55:39 +02:00 |
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14f5051692
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1.0.0-rc.89
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2025-10-01 22:54:40 +02:00 |
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a48d8fb5b9
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1.0.0.rc-88
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2025-10-01 11:18:10 +02:00 |
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53dfb83459
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CI: Build RPMs for sls-det9, but don't upload (handle only via gitea)
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2025-09-23 13:13:19 +02:00 |
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c0bd8e1215
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v1.0.0-rc.82
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2025-09-22 19:49:39 +02:00 |
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c67337cfe1
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v1.0.0-rc.72
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2025-09-08 20:28:59 +02:00 |
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18b50e9472
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v1.0.0-rc.39
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2025-05-14 23:28:10 +02:00 |
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ddf4c75645
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v1.0.0-rc.31
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2025-03-02 13:15:28 +01:00 |
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e5a775b4a3
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version 1.0.0-rc.28
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2024-12-05 16:41:04 +01:00 |
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71290f374a
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version 1.0.0-rc.27
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2024-12-02 21:17:14 +01:00 |
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b3e745a8dd
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version 1.0.0-rc.26
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2024-11-26 16:04:38 +01:00 |
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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b56d3a1461
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FIX CI
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2024-11-17 15:45:15 +01:00 |
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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24bb82c8f7
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Python client is built in CI (no new release)
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2024-10-23 21:13:22 +02:00 |
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631a9d5312
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Fix for pipeline (no new release!)
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2024-10-23 20:05:05 +02:00 |
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36e3a59802
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version 1.0.0-rc.21
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2024-10-23 10:16:37 +02:00 |
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3c556c69c5
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CI: Remove FPGA build from CI
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2024-10-22 08:18:55 +02:00 |
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40c1e3d49f
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version 1.0.0-rc.20
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2024-10-21 13:30:56 +02:00 |
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4ae0668f2f
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Fixes to 8x10g FPGA image and frontend
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2024-10-16 09:12:24 +02:00 |
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ce19996874
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version 1.0.0-rc.17
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2024-10-14 15:03:38 +02:00 |
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b605b95127
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version 1.0.0-rc.16
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2024-10-11 11:11:37 +02:00 |
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3be959f272
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version 1.0.0-rc.14
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2024-10-07 11:56:40 +02:00 |
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e812918e2e
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version 1.0.0-rc.13
|
2024-10-05 13:14:49 +02:00 |
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3e5ed2e9f9
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1.0.0-rc.12 Minor fixes
|
2024-07-08 19:58:27 +02:00 |
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00be0bb224
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1.0.0-rc.12: Fixes to versioning
|
2024-07-06 10:56:54 +02:00 |
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6b5fddf2b7
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Version 1.0.0-rc.12
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2024-07-06 09:34:44 +02:00 |
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3035d9e144
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v1.0.0_rc.11
|
2024-06-30 17:48:35 +02:00 |
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86b3934387
|
Extra metadata in HDF5 writer completed file stream
|
2024-06-05 18:18:12 +02:00 |
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3ef89483e8
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MAX IV experiment day 2 corrections
|
2024-05-23 12:15:36 +02:00 |
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27e17c316d
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Build RPM for DKMS driver
|
2024-05-20 11:40:30 +02:00 |
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2a8fc3a466
|
Minor fixes for dependencies
|
2024-05-19 14:09:00 +02:00 |
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4ca397bd42
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Change the way dependencies are handled
|
2024-05-17 19:19:17 +02:00 |
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91fd44bff7
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Improve release/versioning of Jungfraujoch repository
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2024-05-15 11:29:01 +02:00 |
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5312f3ea6a
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Improvements in building Jungfraujoch
|
2024-05-06 21:28:55 +02:00 |
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809441d0f0
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Move back to DECTRIS flavor of NXmx
|
2024-04-11 16:10:21 +02:00 |
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
|
2024-03-05 20:41:47 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
|
2024-01-27 21:23:56 +01:00 |
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d82bd13917
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Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
|
2023-12-14 22:39:17 +01:00 |
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0b69dfb290
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New REST+OpenAPI interface
|
2023-12-11 12:11:54 +01:00 |
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1798de247b
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Extend FPGA functionality
|
2023-12-09 12:08:39 +01:00 |
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905c26ba88
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CI: Remove JFJOCH_COMPILE_TESTS from cmake directives
|
2023-11-29 10:49:24 +01:00 |
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c5f6119455
|
Remove DataAnalysisPerfTest from CI
|
2023-11-16 13:45:37 +01:00 |
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a17b75862e
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Update CI scripts. Remove retaining .bit files (large and not useful) and remove RHEL7 specific parts.
|
2023-11-01 12:18:37 +01:00 |
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dd002e3d6d
|
FPGA: Build only 100G solution (no bifurcated design)
|
2023-09-07 12:10:38 +02:00 |
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f66fc95ecc
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FPGA: Use 250 Hz for 100 Gbit/s design + adjust TCL scripts
|
2023-08-15 14:39:04 +02:00 |
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7a98766304
|
FPGA: Split receiver and FPGA design directories
|
2023-06-07 21:21:22 +02:00 |
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1757d42182
|
Initial commit
Signed-off-by: Filip Leonarski <filip.leonarski@psi.ch>
|
2023-04-06 11:17:59 +02:00 |
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