CI: Remove FPGA build from CI

This commit is contained in:
2024-10-22 08:18:55 +02:00
parent 0f6d02a878
commit 3c556c69c5

View File

@@ -1,7 +1,6 @@
stages:
- build
- test
- synthesis
- release
build:x86:gcc:
@@ -220,76 +219,6 @@ test:x86:xia2.ssx:
- source /usr/local/dials-v3-17-0/dials_env.sh
- xia2.ssx image=writing_test_master.h5 space_group=P43212 unit_cell=78.551,78.551,36.914,90.000,90.000,90.000
synthesis:vivado_pcie_100g:
stage: synthesis
dependencies: []
variables:
CC: gcc
CXX: g++
rules:
- if: $CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH
- if: $CI_PIPELINE_SOURCE == "push"
changes:
- fpga/hls/*
- fpga/hdl/*
- fpga/scripts/*
- fpga/xdc/*
- fpga/pcie_driver/jfjoch_fpga.h
- if: $CI_COMMIT_MESSAGE =~ /^FPGA/
allow_failure: true
tags:
- vivado
retry: 2
artifacts:
paths:
- "jfjoch_fpga_pcie_100g.mcs"
expire_in: 1 week
script:
- source /opt/rh/gcc-toolset-12/enable
- source /opt/Xilinx/Vivado/2022.1/settings64.sh
- touch jfjoch_fpga_pcie_100g.mcs
- mkdir -p build
- cd build
- /usr/bin/cmake ..
- make -j4 pcie_100g
- mv fpga/jfjoch_fpga_pcie_100g.mcs ..
needs: ["build:x86:gcc", "test:x86:gcc"]
synthesis:vivado_pcie_8x10g:
stage: synthesis
dependencies: []
variables:
CC: gcc
CXX: g++
rules:
- if: $CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH
- if: $CI_PIPELINE_SOURCE == "push"
changes:
- fpga/hls/*
- fpga/hdl/*
- fpga/scripts/*
- fpga/xdc/*
- fpga/pcie_driver/jfjoch_fpga.h
- if: $CI_COMMIT_MESSAGE =~ /^FPGA/
allow_failure: true
tags:
- vivado
retry: 2
artifacts:
paths:
- "jfjoch_fpga_pcie_8x10g.mcs"
expire_in: 1 week
script:
- source /opt/rh/gcc-toolset-12/enable
- source /opt/Xilinx/Vivado/2022.1/settings64.sh
- touch jfjoch_fpga_pcie_8x10g.mcs
- mkdir -p build
- cd build
- /usr/bin/cmake ..
- make -j4 pcie_8x10g
- mv fpga/jfjoch_fpga_pcie_8x10g.mcs ..
needs: [ "build:x86:gcc", "test:x86:gcc" ]
release:
stage: release
rules: