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0b95456d3d
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Adapt PCIe driver and tests for the new frame generator
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2023-09-13 21:44:20 +02:00 |
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496d016c31
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FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets)
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2023-09-13 20:06:09 +02:00 |
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9d01630cfc
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FPGA: load calibration works as dedicated function of the card
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2023-09-12 14:34:42 +02:00 |
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8c3a25a8ad
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FPGA: load calibration operates directly on HBM
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2023-09-11 21:47:29 +02:00 |
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05000bab1f
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FPGA: remove transfer to HBM for the time being
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2023-09-11 20:24:20 +02:00 |
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309dabd32b
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FPGA: Use dedicated struct for address exchange
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2023-09-11 11:19:05 +02:00 |
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6cd8d768ea
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FPGA: save_to_hbm uses dedicated data structure for completion
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2023-09-11 10:50:15 +02:00 |
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48861aafcb
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FPGAAcquisitionDevice: Report HBM size
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2023-09-10 16:38:25 +02:00 |
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175aefc4b8
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FPGA: Save to HBM uses only 2 channels
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2023-09-10 09:54:32 +02:00 |
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929f6c6544
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FPGA: Handle HBM offsets internally in Jungfraujoch logic
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2023-09-09 20:50:41 +02:00 |
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aca1bbda0e
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HLSSimulatedDevice: moving towards continuous HBM representation
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2023-09-09 13:10:06 +02:00 |
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6251c58f32
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FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
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2023-09-08 19:08:37 +02:00 |
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c2eaee6d8a
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FPGA: Save to HBM operates in parallel to host writer
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2023-09-08 13:07:49 +02:00 |
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38df621cf6
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FPGA: Add save to HBM (work in progress)
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2023-09-07 22:15:20 +02:00 |
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347bfd3f2c
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HLSSimulateDevice: Remove reference to UltraRAM
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2023-09-07 21:39:14 +02:00 |
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3aeb3e09ee
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FPGA: Do not load internal packet generator frame via DMA
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2023-09-06 11:57:16 +02:00 |
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caf950f99f
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FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
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2023-09-06 08:19:03 +02:00 |
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a12fc941d5
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JFJochReceiver: Remove host subdirectory
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2023-06-07 21:28:22 +02:00 |
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