 leonarski_f
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4032ce09b8
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FPGA: increase burst length and latency for internal packet generator AXI interface
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2023-09-07 05:54:24 +02:00 |
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leonarski_f
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11696608ca
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FPGA: reduce AXI number of outstainding operations in internal packet generator
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2023-09-06 18:23:36 +02:00 |
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leonarski_f
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0434207882
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FPGA: use full AXI for internal packet generator
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2023-09-06 18:16:44 +02:00 |
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leonarski_f
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3aeb3e09ee
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FPGA: Do not load internal packet generator frame via DMA
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2023-09-06 11:57:16 +02:00 |
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leonarski_f
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caf950f99f
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FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
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2023-09-06 08:19:03 +02:00 |
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leonarski_f
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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