91 lines
3.3 KiB
C++
91 lines
3.3 KiB
C++
// Copyright (2019-2022) Paul Scherrer Institute
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// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
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#include "hls_jfjoch.h"
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void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
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hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_in,
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hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_out,
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ap_uint<512> *frame,
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volatile ap_uint<1> &in_cancel) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=data_out
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#pragma HLS INTERFACE register both axis port=addr_in
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#pragma HLS INTERFACE register both axis port=addr_out
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#pragma HLS INTERFACE m_axi port=frame bundle=frame depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=16 latency=2 num_write_outstanding=2 num_read_outstanding=2
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#pragma HLS INTERFACE ap_none register port=in_cancel
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packet_512_t packet_in;
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packet_512_t packet_out;
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// Read and forward packet #0
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data_in >> packet_in;
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ap_uint<5> modules = ACT_REG_NMODULES(packet_in.data);
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ap_uint<64> mode = ACT_REG_MODE(packet_in.data);
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ap_uint<1> internal_packet_generator = (mode & MODE_INTERNAL_PACKET_GEN) ? 1 : 0;
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ap_uint<32> nframes = ACT_REG_NFRAMES(packet_in.data);
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ap_uint<5> storage_cells = ACT_REG_NSTORAGE_CELLS(packet_in.data);
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ap_uint<1> conversion = (mode & MODE_CONV) ? 1 : 0;
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data_out << packet_in;
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ap_uint<ADDR_STREAM_WIDTH> addr;
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addr_in >> addr;
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addr_out << addr;
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if (conversion) {
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forward_gain:
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for (int i = 0; i < modules * (3 + storage_cells * 3) * (RAW_MODULE_SIZE * 2 / 64); i++) {
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#pragma HLS PIPELINE II=1
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data_in >> packet_in;
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data_out << packet_in;
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}
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}
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if (internal_packet_generator) {
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uint32_t frame_number = 1;
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uint8_t module_number = 0;
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generate_frames:
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while (!in_cancel.read() && (frame_number <= nframes)) {
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for (uint32_t i = 0; i < RAW_MODULE_SIZE * 2 / 64; i++) {
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#pragma HLS PIPELINE II=1
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uint32_t eth_packet = i / 128;
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uint32_t axis_packet = i % 128;
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if (axis_packet == 0)
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addr_out << addr_packet(eth_packet, module_number, frame_number, INT_PKT_GEN_DEBUG,
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INT_PKT_GEN_TIMESTAMP, INT_PKT_GEN_BUNCHID, INT_PKT_GEN_EXPTTIME);
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packet_out.user = 0;
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packet_out.id = 0;
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packet_out.last = (axis_packet == 127) ? 1 : 0;
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packet_out.data = frame[i];
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data_out << packet_out;
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}
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if (module_number == modules - 1) {
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frame_number++;
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module_number = 0;
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} else
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module_number++;
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}
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}
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addr_in >> addr;
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forward_packets:
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while (!addr_last_flag(addr)) {
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#pragma HLS PIPELINE II=1
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data_in >> packet_in;
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data_out << packet_in;
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if (packet_in.last) {
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addr_out << addr;
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addr_in >> addr;
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}
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}
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addr_out << addr;
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data_in >> packet_in;
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data_out << packet_in;
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}
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