Dhanya Thattil
e7879ee365
g2 and m3 round robin ( #559 )
...
* g2 and m3: round robin
2022-10-18 15:51:23 +02:00
Dhanya Thattil
da16c1101c
G2 hdi id ( #521 )
...
* g2: hdi value in fpga is 3 bits, so using appropriate enum for it
* hdi id bits are determined
* fw date changed (g2)
2022-08-23 08:02:11 +02:00
Dhanya Thattil
1bc4994be6
G2parallel ( #514 )
...
* g2: non parallel added
2022-08-16 09:35:39 +02:00
Dhanya Thattil
22b9562629
G2hdi ( #510 )
...
* g2: new hdi values, write hdi value to reg, set slave/master to reg, able to set master from server config file, server command line and client
* print versions for virtual as well
2022-08-16 09:31:13 +02:00
4de7bb51ed
updated all .h files with license notice and copyright notice
2021-10-14 18:10:56 +02:00
ec2a03132a
g2: asic defaults refactored instead of hard coded
2021-09-27 15:31:24 +02:00
a51deda2a4
moduleid for eiger m3 and g2, but set only for g2
2021-09-01 17:06:34 +02:00
334d58c3fd
g2: fix for module id register
2021-08-16 15:38:19 +02:00
ff9eaaf3f3
serialnumber fixed to point to mod id reg
2021-08-11 19:30:25 +02:00
9a777b13bb
g2: dbitpipeline
2021-08-11 18:01:28 +02:00
7a76064223
vetoalg added hits and raw
2021-08-11 16:08:32 +02:00
0dbb6ff512
added module id register
2021-08-11 14:59:53 +02:00
e02493d4e4
veotalg for g2
2021-07-20 14:57:31 +02:00
780d4bfe0a
gotthard2: vetostream (detector: only 3gbe, 10gbe via numudpinterfaces)
2021-07-15 16:21:17 +02:00
8354395f64
wip
2021-07-15 13:44:42 +02:00
a127f8c97a
g2: badchanels moved to a new register base
2021-07-14 16:03:13 +02:00
7c21aa96a9
g2: setting continuous mode frames in naother reg, and when changing from burst to continous
2020-09-18 17:58:39 +02:00
Dhanya Thattil
e8156d412e
G2: continuous internal mode ( #167 )
2020-09-09 10:13:15 +02:00
ca298580f3
badchannels done
2020-07-15 18:24:17 +02:00
0525e374b2
settign veto also configures mac, sending veto data for 10gb only if veto and numinterfaces==2, changed veto entry offset
2020-05-28 10:35:48 +02:00
4300e95a8e
virtual, adding veto command
2020-05-27 14:37:52 +02:00
eea67014b7
gotthard2 with veto data on second interface
2020-05-13 17:50:18 +02:00
671cf45fd7
format slsdetectorservers
2020-05-05 15:23:11 +02:00
134611c638
gotthard2: switching between period and burst period (not delay and burst period), internal frequency depending on timing source (for all except actualtime and measurement time)
2020-03-03 17:49:28 +01:00
Dhanya Thattil
11e7737a2f
gotthard2: timingsource and currentsource features, (timing source external yet to be implemented in fpga to test ( #80 )
2020-02-28 12:45:02 +01:00
e746256653
gotthard2: gain updated
2020-01-21 16:01:38 +01:00
2e78484b61
gotthard2 virtual server sends data
2020-01-21 14:50:31 +01:00
6cfd0f8962
gotthard2: first edit
2020-01-20 12:13:23 +01:00
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
c4675da0c3
m3: reset fixed
2019-11-22 16:40:43 +01:00
d07873ee39
mythen3 and gotthard2: wait request not needed, reset to be implemented
2019-11-22 11:29:24 +01:00
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
Dhanya Thattil
995f0924e5
Commandline ( #66 )
...
* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
2019-10-21 10:29:06 +02:00
be50344b45
set clock divider, phase and get clock freq for gotthard2, priliminary
2019-10-17 16:39:41 +02:00
0f99dd141e
gotthard 2 server test bus
2019-10-01 17:34:52 +02:00
b3ff825ce8
updated gotthard2 api etc
2019-10-01 16:26:42 +02:00
288b59d292
gotthard2 changes for first firmware version
2019-09-26 14:10:11 +02:00
aecf3bb7db
gotthard udp fix
2019-08-26 11:47:28 +02:00
386b6601a8
initial version of gotthard2
2019-08-26 09:59:27 +02:00
