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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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137 lines
5.2 KiB
C
137 lines
5.2 KiB
C
#pragma once
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#define REG_OFFSET (4)
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/* Base addresses 0x1804 0000 ---------------------------------------------*/
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/* Reconfiguration core for readout pll */
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#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
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/* Reconfiguration core for system pll */
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#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
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/* Base addresses 0x1806 0000 ---------------------------------------------*/
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/* General purpose control and status registers */
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#define BASE_CONTROL (0x0000)
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/* Acquisition? TODO */
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#define BASE_ACQUISITION (0x0200)
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/* UDP datagram generator */
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#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
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/* Readout PLL registers --------------------------------------------------*/
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#define READOUT_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_READOUT_PLL) //TODO
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#define READOUT_PLL_RESET_OFST (0)
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#define READOUT_PLL_RESET_MSK (0x00000001 << READOUT_PLL_RESET_OFST)
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/* System PLL registers --------------------------------------------------*/
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#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO
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#define SYSTEM_PLL_RESET_OFST (0)
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#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST)
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/* Control registers --------------------------------------------------*/
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/* Module Control Board Serial Number register */
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#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
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#define MCB_SERIAL_NO_VRSN_OFST (16)
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#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* API Version register */
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#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
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/* Fix pattern register */
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#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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/* Status register */
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#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
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#ifdef VIRTUAL
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#endif
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/* Look at me read only register */
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#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
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/* System status register */
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#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL)
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/* Config RW regiseter */
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#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
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/* Control RW register */
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#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
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#define CONTROL_STRT_ACQSTN_OFST (0)
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#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
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#define CONTROL_STP_ACQSTN_OFST (1)
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#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
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#define CONTROL_CRE_RST_OFST (10)
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#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
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#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
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#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
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#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
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#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
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/* Pattern IO Control 64 bit register */
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#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL)
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#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL)
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/** DTA Offset Register */
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#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
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/* Acquisition registers --------------------------------------------------*/
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//TODO
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/* Triggers left 64bit Register */
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#define GET_CYCLES_LSB_REG (0x10 + BASE_ACQUISITION)
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#define GET_CYCLES_MSB_REG (0x14 + BASE_ACQUISITION)
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/* Frames left 64bit Register */
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#define GET_FRAMES_LSB_REG (0x18 + BASE_ACQUISITION)
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#define GET_FRAMES_MSB_REG (0x1C + BASE_ACQUISITION)
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/* Delay 64bit Write-register */
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#define SET_DELAY_LSB_REG (0x88 + BASE_ACQUISITION)
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#define SET_DELAY_MSB_REG (0x8C + BASE_ACQUISITION)
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/* Cylces 64bit Write-register */
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#define SET_CYCLES_LSB_REG (0x90 + BASE_ACQUISITION)
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#define SET_CYCLES_MSB_REG (0x94 + BASE_ACQUISITION)
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/* Frames 64bit Write-register */
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#define SET_FRAMES_LSB_REG (0x98 + BASE_ACQUISITION)
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#define SET_FRAMES_MSB_REG (0x9C + BASE_ACQUISITION)
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/* Period 64bit Write-register */
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#define SET_PERIOD_LSB_REG (0xA0 + BASE_ACQUISITION)
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#define SET_PERIOD_MSB_REG (0xA4 + BASE_ACQUISITION)
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/* Exptime 64bit Write-register */
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#define SET_EXPTIME_LSB_REG (0xA8 + BASE_ACQUISITION)
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#define SET_EXPTIME_MSB_REG (0xBC + BASE_ACQUISITION) |