mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-26 00:00:02 +02:00
995f0924e5
* WIP * WIP * removed status to string from defs * WIP * WIP * WIP removed unused functions in multi * WIP * print hex in a terrible way * WIP, loadconfig error * WIP, type to string * WIP * fix to conversion * WIP, hostname doesnt work * WIP * WIP * WIP * WIP, threshold * WIP, threshold * WIP * WIP, triggers * WIP, cycles to triggers * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * rx_udsocksize fx, WIP * WIP * WIP * WIP * file index (64 bit), WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * merge * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * WIP * New python mod
104 lines
3.9 KiB
C
104 lines
3.9 KiB
C
#pragma once
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/* Definitions for FPGA*/
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#define REG_OFFSET (4)
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/* cspbase 0x1804 0000 */
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#define BASE_READOUT_PLL (0x000)
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#define BASE_SYSTEM_PLL (0x800)
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#define READOUT_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_READOUT_PLL) //TODO
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#define READOUT_PLL_RESET_OFST (0)
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#define READOUT_PLL_RESET_MSK (0x00000001 << READOUT_PLL_RESET_OFST)
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#define SYSTEM_PLL_RESET_REG (0x1 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO
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#define SYSTEM_PLL_RESET_OFST (0)
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#define SYSTEM_PLL_RESET_MSK (0x00000001 << SYSTEM_PLL_RESET_OFST)
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#define READOUT_PLL_WAIT_REG (0x2 * REG_OFFSET + BASE_READOUT_PLL) //TODO
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#define READOUT_PLL_WAIT_OFST (0)
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#define READOUT_PLL_WAIT_MSK (0x00000001 << READOUT_PLL_WAIT_OFST)
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#define SYSTEM_PLL_WAIT_REG (0x2 * REG_OFFSET + BASE_SYSTEM_PLL) //TODO
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#define SYSTEM_PLL_WAIT_OFST (0)
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#define SYSTEM_PLL_WAIT_MSK (0x00000001 << SYSTEM_PLL_WAIT_OFST)
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/* cspbase 0x1806 0000 */
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#define BASE_CONTROL (0x000)
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#define BASE_ACQUISITION (0x200) //???TODO
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#define BASE_UDP_RAM (0x1000)
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/* Module Control Board Serial Number register */
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#define MCB_SERIAL_NO_REG (0x000 * REG_OFFSET + BASE_CONTROL)
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x001 * REG_OFFSET + BASE_CONTROL)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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#define DETECTOR_TYPE_OFST (24)
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* API Version register */
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#define API_VERSION_REG (0x002 * REG_OFFSET + BASE_CONTROL)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
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/* Fix pattern register */
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#define FIX_PATT_REG (0x003 * REG_OFFSET + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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/* Status register */
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#define STATUS_REG (0x004 * REG_OFFSET + BASE_CONTROL)
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#ifdef VIRTUAL
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#endif
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/* Look at me read only register */
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#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL)
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/** DTA Offset Register */
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#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL)
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/* BASE_ACQUISITION FPGA registers TODO --------------------------------------------------*/
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/* Triggers left 64bit Register */
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#define GET_CYCLES_LSB_REG (0x10 + BASE_ACQUISITION)
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#define GET_CYCLES_MSB_REG (0x14 + BASE_ACQUISITION)
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/* Frames left 64bit Register */
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#define GET_FRAMES_LSB_REG (0x18 + BASE_ACQUISITION)
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#define GET_FRAMES_MSB_REG (0x1C + BASE_ACQUISITION)
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/* Delay 64bit Write-register */
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#define SET_DELAY_LSB_REG (0x88 + BASE_ACQUISITION)
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#define SET_DELAY_MSB_REG (0x8C + BASE_ACQUISITION)
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/* Cylces 64bit Write-register */
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#define SET_CYCLES_LSB_REG (0x90 + BASE_ACQUISITION)
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#define SET_CYCLES_MSB_REG (0x94 + BASE_ACQUISITION)
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/* Frames 64bit Write-register */
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#define SET_FRAMES_LSB_REG (0x98 + BASE_ACQUISITION)
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#define SET_FRAMES_MSB_REG (0x9C + BASE_ACQUISITION)
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/* Period 64bit Write-register */
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#define SET_PERIOD_LSB_REG (0xA0 + BASE_ACQUISITION)
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#define SET_PERIOD_MSB_REG (0xA4 + BASE_ACQUISITION)
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/* Exptime 64bit Write-register */
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#define SET_EXPTIME_LSB_REG (0xA8 + BASE_ACQUISITION)
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#define SET_EXPTIME_MSB_REG (0xBC + BASE_ACQUISITION) |