g2: asic defaults refactored instead of hard coded

This commit is contained in:
maliakal_d 2021-09-27 15:31:24 +02:00
parent dc4e5bb561
commit ec2a03132a
4 changed files with 28 additions and 4 deletions

View File

@ -149,6 +149,10 @@
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DOUT_RDY_SRC_OFST (16)
#define ASIC_CONFIG_DOUT_RDY_SRC_MSK (0x0000000F << ASIC_CONFIG_DOUT_RDY_SRC_OFST)
#define ASIC_CONFIG_DOUT_RDY_DLY_OFST (20)
#define ASIC_CONFIG_DOUT_RDY_DLY_MSK (0x000000FF << ASIC_CONFIG_DOUT_RDY_DLY_OFST)
#define ASIC_CONFIG_DONE_OFST (31)
#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)

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@ -472,8 +472,7 @@ void setupDetector() {
// power on chip
powerChip(1);
// default asic value (masks? what do they mean? TODO)
bus_w(ASIC_CONFIG_REG, DEFAULT_ASIC_CONFIG_VALUE);
setASICDefaults();
setPhase(READOUT_C1, DEFAULT_CLK1_PHASE_DEG, 1);
setDBITPipeline(DEFAULT_DBIT_PIPELINE);
@ -509,6 +508,24 @@ void setupDetector() {
setVetoAlgorithm(DEFAULT_ALGORITHM, ETHERNET_10GB);
}
void setASICDefaults() {
uint32_t addr = ASIC_CONFIG_REG;
// dout ready source
bus_w(addr, bus_r(addr) & ~ASIC_CONFIG_DOUT_RDY_SRC_MSK);
bus_w(addr, bus_r(addr) | ((DEFAULT_ASIC_DOUT_RDY_SRC
<< ASIC_CONFIG_DOUT_RDY_SRC_OFST) &
ASIC_CONFIG_DOUT_RDY_SRC_MSK));
// dout ready delay
bus_w(addr, bus_r(addr) & ~ASIC_CONFIG_DOUT_RDY_DLY_MSK);
bus_w(addr, bus_r(addr) | ((DEFAULT_ASIC_DOUT_RDY_DLY
<< ASIC_CONFIG_DOUT_RDY_DLY_OFST) &
ASIC_CONFIG_DOUT_RDY_DLY_MSK));
// config done
bus_w(addr, bus_r(addr) | ASIC_CONFIG_DONE_MSK);
LOG(logINFO, ("Setting ASIC Defaults (0x%x)\n", bus_r(addr)));
}
int resetToDefaultDacs(int hardReset) {
// reset defaults to hardcoded defaults
if (hardReset) {

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@ -67,7 +67,8 @@
#define DEFAULT_CLK1_PHASE_DEG (270)
#define DEFAULT_DBIT_PIPELINE (1)
#define DEFAULT_ASIC_CONFIG_VALUE (0x80350000)
#define DEFAULT_ASIC_DOUT_RDY_SRC (0x5)
#define DEFAULT_ASIC_DOUT_RDY_DLY (0x3)
#define VETO_DATA_SIZE (160)
typedef struct {

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@ -128,8 +128,10 @@ int resetToDefaultDacs(int hardReset);
int getDefaultDac(enum DACINDEX index, enum detectorSettings sett, int *retval);
int setDefaultDac(enum DACINDEX index, enum detectorSettings sett, int value);
#endif
#ifdef MYTHEN3D
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
void setASICDefaults();
#endif
#ifdef MYTHEN3D
void setADIFDefaults();
#endif
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(JUNGFRAUD)