* round CTB clocks to next closest possible value, added freq measurement
* added time for firmware to measrue actual value after frequency change
* add check for backwards compatibility
* change CTB and XCTB clock values to MHz, TODO: units and validation errors
* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?
* do the same for dbit and adcclk
* added tolerance to exptime, fixed test
* update default values in server defs
* added virtual check in Altera_PLL, update testcases
* change python and pyctbgui to accept and return floating point MHz
* update help and comments
* Dev/ctb clocks fix (#1434)
* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)
* incorrect unit typo
* cmd generation and compiles
* default to MHz, removed space between units for consistency with timers, min and max checks for clks
* in python, but need to change the default to Hz again for clean code and intuition
* allow ints, doubles, implicit conversions
* dont allow raw ints, doubles and implicit conversions
* fixed tests
* added operators for Hz in python
* fix test for min clk for xilinx ctb
* fix test
* fix python tests
* fixed xilinx period and default clks
* test fix
* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb
* removing 3 clock cycle code from xilinx as well
* formatting
* loadpattern before 3 clk cycles code
* actualtime and measurement time to be implemented in 100ns already in fw
* fix tests
* pyzmq dependency forthe tests
* fixed pyctbgui for freq
* insert tolerance check again
* also added tolerance check for patwaittime
* formatting
* minor: rounding test
* removed Rep redundant in ToString for freq
* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary
* minor, and binaries
* minor, default clk vals are 0 but set up at detector setup
* get frequency only for that unit
* tolerance process
* missed in previous commit
* some more changes to exptime and validations
* ctb is probably done
* periodleft and delayleft
* fixed xilinx freq conv as well
* fixed m3 bug, binaries
* xilinx: setup also done in stop server so that the clk is not 0
* missed a test marker
* binaries in
* review fixes, simpler validation of timers in ctb and xilinx ctb
* typo fix
* format
* fix tests
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* added fetch fmt server library
* added first draft of matterhorn
* added enum ReturnCode
* added cpp TCP Interface to slsDetectorServer
* added fmt to workflows
* bug: added std::signal for proper handling of ctr+c
* added compile option to set log level
* WIP
* dont use c project settings when building matterhornserver
* updated logger
* WIP
* WIP
* linked fmt to slsProjectOptions
* solved merge conflict
* some refactoring
* cleaned up logs
* added fmt to workflow
* WIP
* generated register defs from csv file
* oops given in hex
* properly added fmt as a dependency
* add fmt to conda recipe
* some format changes
* dont use public headers of fmt
* WIP
* used CRTP for virtual detector
* WIP
* added udp functions to matterhornserver
* Matterhorn in tostring
* warning unused variable from other PR
* fixed build
* updated cmake
* added Server class usable for all detectors
* removed stopserver
* added some more functions
* wrong overload
* porper cleanup of matterhorn app
* PR Review
* refactored directory structure
* used pause insetad of sleep
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* updated binaries and fixed a warning by moving the usleep_bf to blackfin.c
* suppressed warnings
* cleaned up docs
* renamed function
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
* testing matterhorn1 SPI on altera CTB, works for dummy-chip
* added bf_usleep with proper timing for blackfin
* simplified spi firmware interface, removed write and readstrobe
* define constant for BFIN spi sleep
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* not allowing power names for dac names to prevent duplicate names
* wip
* v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power
* binary in
* dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands
* wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested
* wip. client and xilinx todo
* wip: ctb power works, tests left
* fixed some tests
* added vchip check
* python cmds still left. wip
* fixed xilinx. python left
* wip
* wip. xilinx
* fixed powerchip for ctb
* power all returns all
* configtransceiver is removed
* wip python
* wip
* wip
* wip
* wip
* wip
* wip
* wip xilinx
* wip
* wip
* wip
* pybindings
* fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector
* wip
* fixed tests
* fixes for python api
* wip
* python: moved powerlist to Ctb
* fixed tests to work for powelist in Ctb
* moved signallist, adclist, slowadc, slowadclist to Ctb
* throw approperiate error when no modules added for powers
* added dac test
* fix dac default names and test for dacs
* ctb dacs, yet to do othe rdacs
* dacs should work now even in tests
* run all tests
* DetectorPowers->NamedPowers in ctb
* comments
* removed unnecessary test code
* removed hard coded dac names in python NamedDacs and NamedPowers
* minor
* minor
* fixed error messages
* changed power to be able to set DAC directly, using enable and disable methods with enabled to get
* wip
* wip
* wip. xilinx left
* wip. xilinx
* wip
* wip. compiles
* fixed eiger test
* more fixes
* fixed virtual m3
* fix typos and bugs
* setting power to 0
* set power fixed
* updated server binaries
* minor
* refactoring
* get vchip refactoring
* eiger: unnecessary check for setsettings undefined
* retval pointer for printout
* eiger.wip, mV in boolean
* wip. gotthard2 and m3
* wip. jungfrau
* moench.wip
* compiles.wip
* fix eiger
* m3 fix vthresh
* fix ctband xilinx
* default pwr index = pwr_io
* minor:fn name and highvoltage to local var
* refactor funcs
* minor
* minor
* check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1
* minor
* updated versioning
* review changes: removing validateDACValue and other minor stuff
* binaries in
* wip
* refactored m3 vth
* minor review
* minor review
* m3 serverdac index fix
* minor
* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command
* update docs
* Dhanya's comments
* more Dhanya comments
* refactored
* fixed tests for startpatttern, also clkfrequency not properly used in server
* xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value
* xilinx freq in kHz, updated default values and prints
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
- fix acquire fail in tests (adcreg test)
- roi tests fail after overlapping invalid test and acquire after
- print udp dest mac in server properly
- fixed udp dst list get (server was not sending entry proper size to match proper struct size in client)
- updated server binaries and updated hard links in serverBin
- added documentation regarding gui: zmqport and zmqip in terms of gui, rx_zmqstream
- removed print - probably ended there for debuggung
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
readout speed added to json and h5 master files.
Also fixed master file inconsistencies
Sserver binaries
- update server binaries because readoutspeed needs to be sent to receiver with rx_hostname command
API
- added const to Detector class set/getburstmode
Python
- updated python bindings (burstmode const and roi arguments)
Cmd generation
- added pragma once in Caller.in.h as Caller is included in test files
m3: num channels due to #counters < 3
* workaround for m3 for messed up num channels (client always assumes all counters enabled and adds them to num channels), fix for hdf5
g2: exptime master file inconsistency
- exptime didnt match because of round of when setting burst mode (sets to a different clk divider)
- so updating actual time for all timers (exptime, period, subexptime etc, ) in Module class, get timer values from detector when setting it and then send to receiver to write in master file
ctb image size incorrect:
- write actual size into master file and not the reserved size (digital reduces depending on dbit list and dbit offset)
- added a calculate ctb image size free function in generalData.h that is used there as well as for the tests.
master file inconsistencies
- refactored master attributes writing using templates
- names changed to keep it consistent between json and hdf5 master file (Version, Pixels, Exposure Times, GateDelays, Acquisition Period, etc.)
- datatypes changed to keep it simple where possible: imageSize, dynamicRange, tengiga, quad, readnrows, analog, analogsamples, digital, digitalsamples, dbitreorder, dbitoffset, transceivermask, transeiver, transceiversamples, countermask, gates =>int
- replacing "toString" with arrays, objects etc for eg for scan, rois, etc.
- json header always written (empty dataset or empty brackets)
- hdf5 needs const char* so have to convert strings to it, but taking care that strings exist prior to push_back
- master attributes (redundant string literals->error prone
tests for master file
- suppressed deprecated functions in rapidjson warnings just for the tests
- added slsREceiverSoftware/src to allow access to receiver_defs.h to test binary/hdf5 version
- refactored acquire tests by moving all the acquire tests from individual detector type files to a single one=test-Caller-acquire.cpp
- set some default settings (loadBasicSettings) for a basic acquire at load config part for the test_simulator python scripts. so minimum number of settings for detector to be set for any acquire tests.
- added tests to test master files for json and hdf5= test-Caller-master-attributes.cpp
- added option to add '-m' markers for tests using test_simulator python script
maliakal_d
Martin Mueller
mazzol_a
muelle_m1