* changed api from double to string return for getchipversion, updated python bindings, added to versions command, fixed appropriately to send string from server, fixed tests accordingly to convert the string to int to do the tests
* binary in
* minor
* fixed tests
* updated help for chipversion
* chipversion changed to chipversioninfpga, chipindex, vals and type introduced with string for 3 different types for chip v1.2 and 1.3.
* changed chipversion to chipindex (more apt?) and refactored
* fix without the list.h
* formatting
* scanning string instead of int from server config file for version
* scan works in config now
* chip versions =1.2 divided again
* minor refactoring
* formating
* startup set features allowed with chip index
* fixed existing features
* updated features for chip (dacs not done)
* fixed a test
* fixed another test and removed and unused reg
* fixed check for storage cell feature
* jf binary in
* removed a comment
* formatting
* changed some minor comments specifying v1.1
* minor
* removed comment. minor
* use has feature functions and fix reverse bits using configuration
* minor
* minor
* binary in
* remaining from updated features for chip (dacs not done)
* binary in
* binary in
* moved storage cell delay also to storage cell reg and removed 2 reg field defines that is not used anymore
* binary in
* updated RegisterDefs.h, added trigger and gate option to XCTB
* fix timing mode validation
* fix test case
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* added fetch fmt server library
* added first draft of matterhorn
* added cpp TCP Interface to slsDetectorServer
* bug: added std::signal for proper handling of ctr+c
* added compile option to set log level
* WIP
* dont use c project settings when building matterhornserver
* updated logger
* WIP
* WIP
* linked fmt to slsProjectOptions
* solved merge conflict
* some refactoring
* cleaned up logs
* WIP
* generated register defs from csv file
* oops given in hex
* properly added fmt as a dependency
* some format changes
* WIP
* used CRTP for virtual detector
* WIP
* added udp functions to matterhornserver
* fixed build
* added Server class usable for all detectors
* removed stopserver
* added some more functions
* wrong overload
* porper cleanup of matterhorn app
* PR Review
* refactored directory structure
* added shared memory for aqcuisition status
* implemented bus read and write
* added Matterhorn data class
* modified memory model
* added SPI communication
* moved memory for Bus communication to BucCommunication class
* WIP added HelperFunction for mask conversion
* completed HelperFunctions
* added tests for MatterHorn Helper Functions
* removed shared memory in destructor
* fixed SPI communication
* moved SharedMemory to slsSupportLib
* added toolchain file for cross compilation
* fix constructor for HarwareSPICommunication is public
* update receiver parameters function
* updated mac address
* uploaded matterhorn server binary tracked as lfs
* small fixes from tests on board
* automatically update matterhorn api version when cross compiling binaries
* fix bug in SPI read
* copy to server_directory/bin when cross compiling
* fixed cmake list
* update generate_registerdefs.py
* fixed copy of server binary
* always return error message
* add error log when opening dev/mem
* code review
* fixed eiger, mythen tests for dynamic range
* second Review
* member function getDerived for better readability
* split code into implementation class and actual class doing tcp communication
* added slsWarnings and c++17 compiler option
* added git lfs to workflow
* fix gitea workflows
* bug: add extra clock register
* implement initial checks
* bug: client excpetcs 4 bytes
* refactoring directory structure and rename to .hpp
* check if detector already set up
* missed .h to .hpp
* Code Review 3
* use temmplate value for stopserver
* use internal CMAKE_CROSSCOMPILING variable
* moved boolean stop server flag to DetectorImpl - moving template parameter up
* missed a file
* replace baseclass:: with this
* add Matterhorn server in github workflow
* whatever workflow bug- lets see
* fixed receiving trim bits changed to int64_t
* macOS import guards to have servers compile
* SPI mock since we don't do any actual transfer using the virtual server
* /proc/self/exe alternative for macOS
* round CTB clocks to next closest possible value, added freq measurement
* added time for firmware to measrue actual value after frequency change
* add check for backwards compatibility
* change CTB and XCTB clock values to MHz, TODO: units and validation errors
* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?
* do the same for dbit and adcclk
* added tolerance to exptime, fixed test
* update default values in server defs
* added virtual check in Altera_PLL, update testcases
* change python and pyctbgui to accept and return floating point MHz
* update help and comments
* Dev/ctb clocks fix (#1434)
* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)
* incorrect unit typo
* cmd generation and compiles
* default to MHz, removed space between units for consistency with timers, min and max checks for clks
* in python, but need to change the default to Hz again for clean code and intuition
* allow ints, doubles, implicit conversions
* dont allow raw ints, doubles and implicit conversions
* fixed tests
* added operators for Hz in python
* fix test for min clk for xilinx ctb
* fix test
* fix python tests
* fixed xilinx period and default clks
* test fix
* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb
* removing 3 clock cycle code from xilinx as well
* formatting
* loadpattern before 3 clk cycles code
* actualtime and measurement time to be implemented in 100ns already in fw
* fix tests
* pyzmq dependency forthe tests
* fixed pyctbgui for freq
* insert tolerance check again
* also added tolerance check for patwaittime
* formatting
* minor: rounding test
* removed Rep redundant in ToString for freq
* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary
* minor, and binaries
* minor, default clk vals are 0 but set up at detector setup
* get frequency only for that unit
* tolerance process
* missed in previous commit
* some more changes to exptime and validations
* ctb is probably done
* periodleft and delayleft
* fixed xilinx freq conv as well
* fixed m3 bug, binaries
* xilinx: setup also done in stop server so that the clk is not 0
* missed a test marker
* binaries in
* review fixes, simpler validation of timers in ctb and xilinx ctb
* typo fix
* format
* fix tests
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* added fetch fmt server library
* added first draft of matterhorn
* added enum ReturnCode
* added cpp TCP Interface to slsDetectorServer
* added fmt to workflows
* bug: added std::signal for proper handling of ctr+c
* added compile option to set log level
* WIP
* dont use c project settings when building matterhornserver
* updated logger
* WIP
* WIP
* linked fmt to slsProjectOptions
* solved merge conflict
* some refactoring
* cleaned up logs
* added fmt to workflow
* WIP
* generated register defs from csv file
* oops given in hex
* properly added fmt as a dependency
* add fmt to conda recipe
* some format changes
* dont use public headers of fmt
* WIP
* used CRTP for virtual detector
* WIP
* added udp functions to matterhornserver
* Matterhorn in tostring
* warning unused variable from other PR
* fixed build
* updated cmake
* added Server class usable for all detectors
* removed stopserver
* added some more functions
* wrong overload
* porper cleanup of matterhorn app
* PR Review
* refactored directory structure
* used pause insetad of sleep
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* updated binaries and fixed a warning by moving the usleep_bf to blackfin.c
* suppressed warnings
* cleaned up docs
* renamed function
---------
Co-authored-by: Alice <alice.mazzoleni@psi.ch>
* testing matterhorn1 SPI on altera CTB, works for dummy-chip
* added bf_usleep with proper timing for blackfin
* simplified spi firmware interface, removed write and readstrobe
* define constant for BFIN spi sleep
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* not allowing power names for dac names to prevent duplicate names
* wip
* v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power
* binary in
* dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands
* wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested
* wip. client and xilinx todo
* wip: ctb power works, tests left
* fixed some tests
* added vchip check
* python cmds still left. wip
* fixed xilinx. python left
* wip
* wip. xilinx
* fixed powerchip for ctb
* power all returns all
* configtransceiver is removed
* wip python
* wip
* wip
* wip
* wip
* wip
* wip
* wip xilinx
* wip
* wip
* wip
* pybindings
* fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector
* wip
* fixed tests
* fixes for python api
* wip
* python: moved powerlist to Ctb
* fixed tests to work for powelist in Ctb
* moved signallist, adclist, slowadc, slowadclist to Ctb
* throw approperiate error when no modules added for powers
* added dac test
* fix dac default names and test for dacs
* ctb dacs, yet to do othe rdacs
* dacs should work now even in tests
* run all tests
* DetectorPowers->NamedPowers in ctb
* comments
* removed unnecessary test code
* removed hard coded dac names in python NamedDacs and NamedPowers
* minor
* minor
* fixed error messages
* changed power to be able to set DAC directly, using enable and disable methods with enabled to get
* wip
* wip
* wip. xilinx left
* wip. xilinx
* wip
* wip. compiles
* fixed eiger test
* more fixes
* fixed virtual m3
* fix typos and bugs
* setting power to 0
* set power fixed
* updated server binaries
* minor
* refactoring
* get vchip refactoring
* eiger: unnecessary check for setsettings undefined
* retval pointer for printout
* eiger.wip, mV in boolean
* wip. gotthard2 and m3
* wip. jungfrau
* moench.wip
* compiles.wip
* fix eiger
* m3 fix vthresh
* fix ctband xilinx
* default pwr index = pwr_io
* minor:fn name and highvoltage to local var
* refactor funcs
* minor
* minor
* check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1
* minor
* updated versioning
* review changes: removing validateDACValue and other minor stuff
* binaries in
* wip
* refactored m3 vth
* minor review
* minor review
* m3 serverdac index fix
* minor
* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command
* update docs
* Dhanya's comments
* more Dhanya comments
* refactored
* fixed tests for startpatttern, also clkfrequency not properly used in server
* xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value
* xilinx freq in kHz, updated default values and prints
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
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