detectors/slsDetectorPackage
24
1
Fork 0
mirror of https://github.com/slsdetectorgroup/slsDetectorPackage.git synced 2026-02-13 14:18:46 +01:00
Code Issues Actions 4 Packages Releases Activity

Pattern unification & Matterhorn Changes (#1303)
Some checks failed
Build on RHEL9 / build (push) Failing after 3m7s
Details
Build on RHEL8 / build (push) Failing after 4m58s
Details

Browse Source 
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout

* fix fifo fill level range bug

* updated ctb RegDefs, increased size of fifo fill level register

* added register to read the firmware git hash

* ctb: added altchip_id read register

* start with unification of pattern machinery for xctb, ctb, mythen

* udate addrs for d-server internal matterhorn startup

* update xctb reg defs

* move pattern loopdef start

* added zero trimbits to matterhorn config

* Revert "added zero trimbits to matterhorn config"

This reverts commit 7c347badd5.

* added adjustable clocks on Xilinx-CTB

* added support for fractional dividers of runclk

* XCTB: make frequencies adjustable from python gui

* update docs

* added support for patternstart command to XCTB

* XCTB: map pattern_ram directly into memory, removed rw strobe

* refactor Mythen pattern control addresses

* test altera ctb with common addresses, removed ifdefs

* change ordering of regdefs

* updated python help for dbitclk, adcclk and runclk (khz)

* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side

* will not be anymore in developer branch

* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code

* bug: mixing && for &

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
This commit is contained in:
Martin Mueller
2025-09-17 17:28:17 +02:00
committed by GitHub
parent 6e006665ef
commit e7a91d38f2
33 changed files with 795 additions and 951 deletions
Download Patch File Download Diff File Expand all files Collapse all files

357
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
View File

@@ -5,6 +5,7 @@
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 1
#define REG_OFFSET (2)
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
@@ -65,8 +66,8 @@
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
/* Register containing the git hash of the FPGA firmware */
#define FIRMWARE_GIT_HASH_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
@@ -119,7 +120,7 @@
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_REG (0x0B << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
@@ -128,24 +129,24 @@
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
#define TIME_FROM_START_LSB_REG (0x97 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x98 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
#define DELAY_LEFT_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Triggers Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_LSB_REG (0x93 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x94 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
// #define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
@@ -160,34 +161,34 @@
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
#define DATA_IN_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
#define PATTERN_OUT_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x81 << MEM_MAP_SHIFT)
/* Frame number of next acquisition register (64 bit register) */
#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x22 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x23 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_LSB_REG (0x99 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x9A << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_LSB_REG (0x9B << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x9C << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_REG (0x18 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* FIFO Transceiver In Status RO register */
#define FIFO_TIN_STATUS_REG (0x30 << MEM_MAP_SHIFT)
#define FIFO_TIN_STATUS_REG (0x1A << MEM_MAP_SHIFT)
#define FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST (4)
#define FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST (5)
@@ -198,23 +199,54 @@
#define FIFO_TIN_STATUS_FIFO_EMPTY_4_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
/* FIFO Transceiver Fill level RO register */
#define FIFO_TIN_FILL_REG (0x25 << MEM_MAP_SHIFT)
#define FIFO_TIN_FILL_FIFO_1_OFST (0)
#define FIFO_TIN_FILL_FIFO_1_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__1_OFST)
#define FIFO_TIN_FILL_FIFO_2_OFST (16)
#define FIFO_TIN_FILL_FIFO_2_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__2_OFST)
/* FIFO ADC Fill level RO register */
#define FIFO_ADC_FILL_REG (0x26 << MEM_MAP_SHIFT)
#define FIFO_ADC_FILL_FIFO_OFST (0)
#define FIFO_ADC_FILL_FIFO_MSK (0x00003FFF << FIFO_ADC_FILL_FIFO_OFST)
/* Enable continuos readout register */
#define CONTINUOUS_RO_ENABLE_REG (0x27 << MEM_MAP_SHIFT)
#define CONTINUOUS_RO_ADC_ENABLE_OFST (0)
#define CONTINUOUS_RO_TIN_ENABLE_OFST (1)
#define CONTINUOUS_RO_DBIT_ENABLE_OFST (2)
#define CONTINUOUS_RO_ADC_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_ADC_ENABLE_OFST)
#define CONTINUOUS_RO_TIN_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_TIN_ENABLE_OFST)
#define CONTINUOUS_RO_DBIT_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_DBIT_ENABLE_OFST)
#define DBIT_INJECT_COUNTER_ENA_OFST (3) // continuously injects fake-data into the dbit fifo when enabled.
#define DBIT_INJECT_COUNTER_ENA_MSK (0x00000001 << DBIT_INJECT_COUNTER_ENA_OFST)
#define DBIT_INJECT_COUNTER_CLKDIV_OFST (8) // Additional clock divider for fake-data injection
#define DBIT_INJECT_COUNTER_CLKDIV_MSK (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
/* 64-bit FPGA chip ID. Unique for every device. read-only */
#define FPGA_chipID_0_REG (0x28 << MEM_MAP_SHIFT)
#define FPGA_chipID_1_REG (0x29 << MEM_MAP_SHIFT)
/* FIFO Transceiver In 64 bit RO register */
#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
#define FIFO_TIN_MSB_REG (0x32 << MEM_MAP_SHIFT)
#define FIFO_TIN_LSB_REG (0x1B << MEM_MAP_SHIFT)
#define FIFO_TIN_MSB_REG (0x1C << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_REG (0x1D << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FILL_OFST (0)
#define FIFO_DIN_STATUS_FIFO_FILL_MSK (0x00003FFF)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
#define FIFO_DIN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_REG (0x20 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
@@ -230,7 +262,7 @@
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_REG (0x21 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
@@ -240,7 +272,7 @@
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_REG (0x22 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
@@ -248,7 +280,7 @@
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_REG (0x23 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
@@ -260,7 +292,7 @@
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_REG (0x24 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
@@ -273,46 +305,8 @@
#define DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST (14)
#define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
/* UDP Port RW register */
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
/* Receiver Mac Address 64 bit RW register */
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
/* Detector/ Transmitter Mac Address 64 bit RW register */
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
/* Detector/ Transmitter IP Address RW register */
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
/* Detector/ Transmitter IP Checksum RW register */
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_REG (0x2D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
@@ -327,7 +321,7 @@
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_REG (0x2E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
@@ -335,7 +329,7 @@
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_REG (0x2F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
@@ -375,10 +369,10 @@
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
#define PLL_PARAM_REG (0x30 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_REG (0x31 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
@@ -391,7 +385,7 @@
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_REG (0x88 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
@@ -401,70 +395,31 @@
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_REG (0x89 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
/** Pattern Loop and Wait Definitions, 5 regs each */
#define PATTERN_LOOPDEF_BASE (0xA0 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_ADDR_WORD_OFST (0)
#define PATTERN_LOOP_ITERATION_WORD_OFST (1)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
/* Pattern Loop 1 Address RW regiser */
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
/* Pattern Loop 2 Address RW regiser */
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
/* Pattern Wait 0 RW regiser */
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
// FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001FFF << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STP_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
#define SAMPLES_REG (0x32 << MEM_MAP_SHIFT)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
@@ -472,7 +427,7 @@
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
/** Power RW register */
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_REG (0x33 << MEM_MAP_SHIFT)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
@@ -480,25 +435,25 @@
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
/* Number of samples from transceiver RW register */
#define SAMPLES_TRANSCEIVER_REG (0x5F << MEM_MAP_SHIFT)
#define SAMPLES_TRANSCEIVER_REG (0x34 << MEM_MAP_SHIFT)
#define SAMPLES_TRANSCEIVER_OFST (0)
#define SAMPLES_TRANSCEIVER_MSK (0x0000FFFF << SAMPLES_TRANSCEIVER_OFST)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
#define DELAY_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Triggers 64 bit RW register */
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
#define CYCLES_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
#define FRAMES_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
#define PERIOD_LSB_REG (0x93 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x94 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
// #define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
@@ -513,33 +468,15 @@
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
/* Pattern IO Clock Control 64 bit RW regiser
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
* When bit n disabled (0), Dio[n] driven by its pattern output */
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_LSB_REG (0x8A << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x8B << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
#define PATTERN_IN_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x83 << MEM_MAP_SHIFT)
/* Readout enable RW register */
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_REG (0x3C << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
@@ -550,7 +487,7 @@
(0x0000000F << READOUT_10G_ENABLE_TRNSCVR_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_REG (0x3E << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
@@ -558,7 +495,7 @@
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_REG (0x3F << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
@@ -574,87 +511,21 @@
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
#define PIN_DELAY_1_REG (0x40 << MEM_MAP_SHIFT)
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
#define PATTERN_MASK_LSB_REG (0x84 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x85 << MEM_MAP_SHIFT)
/** Pattern Set 64 bit RW regiser */
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
/* Pattern Loop 3 Address RW regiser */
#define PATTERN_LOOP_3_ADDR_REG (0x84 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_3_ADDR_STP_OFST)
/* Pattern Loop 3 Iteration RW regiser */
#define PATTERN_LOOP_3_ITERATION_REG (0x85 << MEM_MAP_SHIFT)
/* Pattern Loop 4 Address RW regiser */
#define PATTERN_LOOP_4_ADDR_REG (0x86 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_4_ADDR_STP_OFST)
/* Pattern Loop 4 Iteration RW regiser */
#define PATTERN_LOOP_4_ITERATION_REG (0x87 << MEM_MAP_SHIFT)
/* Pattern Loop 5 Address RW regiser */
#define PATTERN_LOOP_5_ADDR_REG (0x88 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_5_ADDR_STP_OFST)
/* Pattern Loop 5 Iteration RW regiser */
#define PATTERN_LOOP_5_ITERATION_REG (0x89 << MEM_MAP_SHIFT)
/* Pattern Wait 3 RW regiser */
#define PATTERN_WAIT_3_ADDR_REG (0x8A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_3_ADDR_OFST (0)
#define PATTERN_WAIT_3_ADDR_MSK (0x00001FFF << PATTERN_WAIT_3_ADDR_OFST)
/* Pattern Wait 4 RW regiser */
#define PATTERN_WAIT_4_ADDR_REG (0x8B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_4_ADDR_OFST (0)
#define PATTERN_WAIT_4_ADDR_MSK (0x00001FFF << PATTERN_WAIT_4_ADDR_OFST)
/* Pattern Wait 5 RW regiser */
#define PATTERN_WAIT_5_ADDR_REG (0x8C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_5_ADDR_OFST (0)
#define PATTERN_WAIT_5_ADDR_MSK (0x00001FFF << PATTERN_WAIT_5_ADDR_OFST)
/* Pattern Wait Timer 3 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_3_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_3_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Pattern Wait Timer 4 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_4_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_4_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 5 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
#define PATTERN_SET_LSB_REG (0x86 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x87 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SLOW_DATA_REG (0x93 << MEM_MAP_SHIFT)
#define ADC_SLOW_DATA_REG (0x41 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value Config register */
#define ADC_SLOW_CFG_REG (0x94 << MEM_MAP_SHIFT)
#define ADC_SLOW_CFG_REG (0x42 << MEM_MAP_SHIFT)
/** Read back CFG Register */
#define ADC_SLOW_CFG_RB_OFST (2)
#define ADC_SLOW_CFG_RB_MSK (0x00000001 << ADC_SLOW_CFG_RB_OFST)
@@ -733,7 +604,7 @@
((0x1 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
/* Slow ADC SPI Value Control register */
#define ADC_SLOW_CTRL_REG (0x95 << MEM_MAP_SHIFT)
#define ADC_SLOW_CTRL_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_SLOW_CTRL_STRT_OFST (0)
#define ADC_SLOW_CTRL_STRT_MSK (0x00000001 << ADC_SLOW_CTRL_STRT_OFST)

75
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@@ -348,68 +348,21 @@
#define PATTERN_SET_LSB_REG (0x44 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_SET_MSB_REG (0x45 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait Timer 0 64bit RW Register */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x61 * REG_OFFSET + BASE_PATTERN_CONTROL)
/** Pattern Loop and Wait Definitions, 5 regs each */
#define PATTERN_LOOPDEF_BASE (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (0)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (1)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_LOOP_ITERATION_WORD_OFST (3)
#define PATTERN_LOOP_ADDR_WORD_OFST (4)
/* Pattern Wait 0 RW Register*/
#define PATTERN_WAIT_0_ADDR_REG (0x62 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
/* Pattern Loop 0 Iteration RW Register */
#define PATTERN_LOOP_0_ITERATION_REG (0x63 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Wait Timer 1 64bit RW Register */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x65 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x66 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 1 RW Register*/
#define PATTERN_WAIT_1_ADDR_REG (0x67 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Loop 1 Iteration RW Register */
#define PATTERN_LOOP_1_ITERATION_REG (0x68 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 1 Address RW Register */
#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Wait Timer 2 64bit RW Register */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x6A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x6B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 2 RW Register*/
#define PATTERN_WAIT_2_ADDR_REG (0x6C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Pattern Loop 2 Iteration RW Register */
#define PATTERN_LOOP_2_ITERATION_REG (0x6D * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001FFF << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STP_OFST)
/* Pattern RAM registers --------------------------------------------------*/

12
slsDetectorServers/slsDetectorServer/include/XILINX_PLL.h Normal file
View File

@@ -0,0 +1,12 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include <stdbool.h>
#include <stdint.h>
void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq);
uint32_t XILINX_PLL_getFrequency(uint32_t clkIDX);
bool XILINX_PLL_isLocked();
void XILINX_PLL_reset();
void XILINX_PLL_waitForLock();
void XILINX_PLL_load();

2
slsDetectorServers/slsDetectorServer/include/arm64.h
View File

@@ -6,7 +6,9 @@
#include <sys/types.h>
void bus_w(u_int32_t offset, u_int32_t data);
void bus_w_csp2(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
u_int32_t bus_r_csp2(u_int32_t offset);
uint64_t getU64BitReg(int aLSB, int aMSB);
void setU64BitReg(uint64_t value, int aLSB, int aMSB);
u_int32_t readRegister(u_int32_t offset);

2
slsDetectorServers/slsDetectorServer/include/loadPattern.h
View File

@@ -58,7 +58,7 @@ uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
#ifdef MYTHEN3D
#if defined(MYTHEN3D) || defined(XILINX_CHIPTESTBOARDD)
void startPattern();
#endif
char *getPatternFileName();

7
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
View File

@@ -518,8 +518,6 @@ int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);
void setADCPipeline(int val);
int getADCPipeline();
@@ -529,6 +527,11 @@ int setLEDEnable(int enable);
void setDigitalIODelay(uint64_t pinMask, int delay);
#endif
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
#endif
// jungfrau/moench specific - powerchip, autocompdisable, clockdiv, asictimer,
// clock, pll, flashing firmware
#if defined(MOENCHD)

200
slsDetectorServers/slsDetectorServer/src/XILINX_PLL.c Normal file
View File

@@ -0,0 +1,200 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "XILINX_PLL.h"
#include "arm64.h"
#include "clogger.h"
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
// https://docs.amd.com/r/en-US/pg065-clk-wiz/Register-Space (simplified, we
// leave some things away)
// clang-format off
#define XILINX_PLL_INPUT_FREQ (100000) // 100 MHz
#define XILINX_PLL_MIN_FREQ (10000)
#define XILINX_PLL_MAX_FREQ (250000)
#define XILINX_PLL_MAX_CLK_DIV (256)
#define XILINX_PLL_NUM_CLKS (7)
#define XILINX_PLL_MAX_NUM_CLKS_FOR_GET (3)
#define XILINX_PLL_STEP_SIZE (125)
#define XILINX_PLL_HALF_STEP_SIZE (62)
#define XILINX_PLL_BASE_ADDR (0x0)
#define XILINX_PLL_MEASURE_BASE_ADDR0 (0x1000) // added externally, not part of CLKWIZ core for clks 0 and 1
#define XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS (2)
#define XILINX_PLL_MEASURE_BASE_ADDR1 (0x2000) // for clks 2 to 6
#define XILINX_PLL_MEASURE_WIDTH (8) // per clock
#define XILINX_PLL_RESET_REG (0x000)
#define XILINX_PLL_RESET_VAL (0xA)
#define XILINX_PLL_STATUS_REG (0x004)
#define XILINX_PLL_STATUS_LOCKED_OFST (0)
#define XILINX_PLL_STATUS_LOCKED_MSK (0x00000001 << XILINX_PLL_STATUS_LOCKED_OFST)
#define XILINX_PLL_CLKCONFIG_REG (XILINX_PLL_BASE_ADDR + 0x200)
#define XILINX_PLL_DIVCLK_DIVIDE_OFST (0)
#define XILINX_PLL_DIVCLK_DIVIDE_MSK (0x000000FF << XILINX_PLL_DIVCLK_DIVIDE_OFST)
#define XILINX_PLL_CLKFBOUT_MULT_OFST (8)
#define XILINX_PLL_CLKFBOUT_MULT_MSK (0x000000FF << XILINX_PLL_CLKFBOUT_MULT_OFST)
#define XILINX_PLL_CLKFBOUT_FRAC_OFST (16)
#define XILINX_PLL_CLKFBOUT_FRAC_MSK (0x000003FF << XILINX_PLL_CLKFBOUT_FRAC_OFST)
// The value from 0 to 875 representing the fractional multiplied by 1000
#define XILINX_PLL_CLKFBOUT_FRAC_MAX_VAL (875)
#define XILINX_PLL_CLKCONFIG_BASE_ADDR (XILINX_PLL_BASE_ADDR + 0x208)
#define XILINX_PLL_CLKCONFIG_WIDTH (3 * 4) // per clock (7 clocks)
#define XILINX_PLL_CLK_DIV_REG_OFST (0)
#define XILINX_PLL_CLK_DIV_DIVIDE_OFST (0)
#define XILINX_PLL_CLK_DIV_DIVIDE_MSK (0x000000FF << XILINX_PLL_CLK_DIV_DIVIDE_OFST)
#define XILINX_PLL_CLK_DIV_FRAC_OFST (8) // works on IDX 0 only
#define XILINX_PLL_CLK_DIV_FRAC_MSK (0x000003FF << XILINX_PLL_CLK_DIV_FRAC_OFST)
#define XILINX_PLL_CLK_PHASE_REG_OFST (4) // signed num for +/- phase
#define XILINX_PLL_CLK_PHASE_OFST (0)
#define XILINX_PLL_CLK_PHASE_MSK (0x0000FFFF << XILINX_PLL_CLK_PHASE_OFST)
#define XILINX_PLL_CLK_DUTY_REG_OFST (8) // (in %) * 1000
#define XILINX_PLL_CLK_DUTY_OFST (0)
#define XILINX_PLL_CLK_DUTY_MSK (0x0000FFFF << XILINX_PLL_CLK_DUTY_OFST)
#define XILINX_PLL_LOAD_REG (0x25C)
#define XILINX_PLL_LOAD_RECONFIGURE_OFST (0) // load and reconfigure state machine
#define XILINX_PLL_LOAD_RECONFIGURE_MSK (0x00000001 << XILINX_PLL_LOAD_RECONFIGURE_OFST)
#define XILINX_PLL_LOAD_FROM_REGS_OFST (1) // 0 for default values as compiled into firmware
#define XILINX_PLL_LOAD_FROM_REGS_MSK (0x00000001 << XILINX_PLL_LOAD_FROM_REGS_OFST)
// clang-format on
// freq in kHz !!
void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return;
}
if (freq < XILINX_PLL_MIN_FREQ || freq > XILINX_PLL_MAX_FREQ) {
LOG(logERROR, ("XILINX_PLL: Frequency %d kHz is out of range\n", freq));
return;
}
// calculate base clock frequency
uint32_t global_reg = bus_r_csp2(XILINX_PLL_CLKCONFIG_REG);
#ifdef VIRTUAL
global_reg = 3073;
#endif
uint32_t clkfbout_mult = ((global_reg & XILINX_PLL_CLKFBOUT_MULT_MSK) >>
XILINX_PLL_CLKFBOUT_MULT_OFST);
uint32_t clkfbout_frac = ((global_reg & XILINX_PLL_CLKFBOUT_FRAC_MSK) >>
XILINX_PLL_CLKFBOUT_FRAC_OFST);
uint32_t divclk_divide = ((global_reg & XILINX_PLL_DIVCLK_DIVIDE_MSK) >>
XILINX_PLL_DIVCLK_DIVIDE_OFST);
uint32_t base_clk_freq = clkfbout_mult * XILINX_PLL_INPUT_FREQ;
base_clk_freq += (clkfbout_frac * XILINX_PLL_INPUT_FREQ /
XILINX_PLL_CLKFBOUT_FRAC_MAX_VAL);
base_clk_freq /= divclk_divide;
// calcualte clock divider
uint32_t clk_div = base_clk_freq / freq;
if (clk_div < 1 || clk_div > XILINX_PLL_MAX_CLK_DIV) {
LOG(logERROR,
("XILINX_PLL: Invalid clock divider, need to change base clock\n"));
return;
}
uint32_t clk_div_frac = 0;
// the first clock supports fractional division, increase the precision for
// that one fractional divide is not allowed in fixed or dynamic phase shift
// mode !!!!
if (clk_index == 0) {
float clk_div_frac_f =
(float)base_clk_freq / freq - clk_div; // eg. 2.333 => 0.333
clk_div_frac = (uint32_t)round(clk_div_frac_f * 1000); // 0.333 => 333
clk_div_frac = ((clk_div_frac + XILINX_PLL_HALF_STEP_SIZE) /
XILINX_PLL_STEP_SIZE) *
XILINX_PLL_STEP_SIZE; // round to multiples of step size,
// 333 = > 375
if (clk_div_frac == 1000) {
clk_div_frac = 0;
clk_div++;
}
}
LOG(logINFOBLUE, ("XILINX_PLL: Setting clock divider to %u.%u\n", clk_div,
clk_div_frac));
uint32_t clk_addr = XILINX_PLL_CLKCONFIG_BASE_ADDR +
clk_index * XILINX_PLL_CLKCONFIG_WIDTH +
XILINX_PLL_CLK_DIV_REG_OFST;
uint32_t clk_config_val = ((clk_div << XILINX_PLL_CLK_DIV_DIVIDE_OFST) &
XILINX_PLL_CLK_DIV_DIVIDE_MSK) |
((clk_div_frac << XILINX_PLL_CLK_DIV_FRAC_OFST) &
XILINX_PLL_CLK_DIV_FRAC_MSK);
bus_w_csp2(clk_addr, clk_config_val);
XILINX_PLL_load();
XILINX_PLL_waitForLock();
// wait for firmware to measure the actual frequency
usleep(2 * 1000 * 1000);
}
uint32_t XILINX_PLL_getFrequency(uint32_t clk_index) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return 0;
}
if (clk_index > XILINX_PLL_MAX_NUM_CLKS_FOR_GET) {
LOG(logERROR,
("XILINX_PLL: get frequency not implemented for this clock %d\n",
clk_index));
return 0;
}
uint32_t base_addr = XILINX_PLL_MEASURE_BASE_ADDR0;
if (clk_index >= XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS) {
clk_index -= XILINX_PLL_MEASURE_BASE_ADDR0_MAX_CLKS;
base_addr = XILINX_PLL_MEASURE_BASE_ADDR1;
}
uint32_t addr = base_addr + clk_index * XILINX_PLL_MEASURE_WIDTH;
uint32_t counter_val = bus_r_csp2(addr);
// Hz => round to nearest kHz
uint32_t freq_kHz = (counter_val + 500) / 1000; // round to nearest kHz
return freq_kHz;
}
bool XILINX_PLL_isLocked() {
uint32_t status = bus_r_csp2(XILINX_PLL_BASE_ADDR + XILINX_PLL_STATUS_REG);
return ((status & XILINX_PLL_STATUS_LOCKED_MSK) >>
XILINX_PLL_STATUS_LOCKED_OFST);
}
void XILINX_PLL_reset() {
bus_w_csp2(XILINX_PLL_BASE_ADDR + XILINX_PLL_RESET_REG,
XILINX_PLL_RESET_VAL);
}
void XILINX_PLL_load() {
bus_w_csp2(
XILINX_PLL_BASE_ADDR + XILINX_PLL_LOAD_REG,
(XILINX_PLL_LOAD_RECONFIGURE_MSK | XILINX_PLL_LOAD_FROM_REGS_MSK));
}
void XILINX_PLL_waitForLock() {
#ifdef VIRTUAL
return;
#endif
int timeout_us = 10 * 1000;
int count = 500;
while (count > 0) {
usleep(timeout_us);
if (XILINX_PLL_isLocked())
return;
count--;
}
LOG(logERROR, ("XILINX_PLL: Timeout waiting for PLL to lock (%d ms)\n",
(count * timeout_us) / 1000));
}

27
slsDetectorServers/slsDetectorServer/src/arm64.c
View File

@@ -13,11 +13,14 @@
/* global variables */
#define CSP0 (0xB0080000)
#define CSP1 (0xB0050000) // udp
#define MEM_SIZE_CSP0 (0x10000)
#define CSP2 (0xA0000000)
#define MEM_SIZE_CSP0 (0x20000)
#define MEM_SIZE_CSP1 (0x2000) // smaller size for udp
#define MEM_SIZE_CSP2 (0x4000)
u_int32_t *csp0base = 0;
u_int32_t *csp1base = 0;
u_int32_t *csp2base = 0;
void bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
@@ -31,6 +34,18 @@ u_int32_t bus_r(u_int32_t offset) {
return *ptr1;
}
void bus_w_csp2(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp2base + offset / (sizeof(u_int32_t)));
*ptr1 = data;
}
u_int32_t bus_r_csp2(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp2base + offset / (sizeof(u_int32_t)));
return *ptr1;
}
uint64_t getU64BitReg(int aLSB, int aMSB) {
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
@@ -51,12 +66,12 @@ u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
int mapCSP0(void) {
LOG(logINFO, ("Mapping memory\n"));
u_int32_t csps[2] = {CSP0, CSP1};
u_int32_t **cspbases[2] = {&csp0base, &csp1base};
u_int32_t memsize[2] = {MEM_SIZE_CSP0, MEM_SIZE_CSP1};
char names[2][10] = {"csp0base", "csp1base"};
u_int32_t csps[3] = {CSP0, CSP1, CSP2};
u_int32_t **cspbases[3] = {&csp0base, &csp1base, &csp2base};
u_int32_t memsize[3] = {MEM_SIZE_CSP0, MEM_SIZE_CSP1, MEM_SIZE_CSP2};
char names[3][10] = {"csp0base", "csp1base", "csp2base"};
for (int i = 0; i < 2; ++i) {
for (int i = 0; i < 3; ++i) {
// if not mapped
if (*cspbases[i] == 0) {
LOG(logINFO, ("\tMapping memory for %s\n", names[i]));

357
slsDetectorServers/slsDetectorServer/src/loadPattern.c
View File

@@ -13,7 +13,7 @@
extern enum TLogLevel trimmingPrint;
extern uint32_t clkDivider[];
#endif
#ifdef CHIPTESTBOARDD
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
extern uint32_t clkFrequency[];
#endif
@@ -54,27 +54,12 @@ void initializePatternWord() {
memset(virtual_pattern, 0, sizeof(virtual_pattern));
}
#endif
#endif
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
uint64_t validate_readPatternIOControl() {
#if defined(CHIPTESTBOARDD)
return getU64BitReg(PATTERN_IO_CNTRL_LSB_REG, PATTERN_IO_CNTRL_MSB_REG);
#elif defined(XILINX_CHIPTESTBOARDD)
return (uint64_t)(bus_r(PINIOCTRLREG));
#endif
}
int validate_writePatternIOControl(char *message, uint64_t arg) {
// validate input
#ifdef XILINX_CHIPTESTBOARDD
if (arg > BIT32_MSK) {
strcpy(message, "Could not set pattern IO Control. Must be 32 bit for "
"this detector\n");
LOG(logERROR, (message));
return FAIL;
}
#endif
writePatternIOControl(arg);
@@ -95,15 +80,9 @@ int validate_writePatternIOControl(char *message, uint64_t arg) {
}
void writePatternIOControl(uint64_t word) {
#ifdef CHIPTESTBOARDD
LOG(logINFO,
("Setting Pattern I/O Control: 0x%llx\n", (long long int)word));
setU64BitReg(word, PATTERN_IO_CNTRL_LSB_REG, PATTERN_IO_CNTRL_MSB_REG);
#elif defined(XILINX_CHIPTESTBOARDD)
uint32_t val = (uint32_t)word;
LOG(logINFO, ("Setting Pattern I/O Control: 0x%x\n", val));
bus_w(PINIOCTRLREG, val);
#endif
}
#endif
@@ -122,7 +101,7 @@ int validate_readPatternWord(char *message, int addr, uint64_t *word) {
}
uint64_t readPatternWord(int addr) {
#ifdef MYTHEN3D
#if defined(MYTHEN3D) || defined(XILINX_CHIPTESTBOARDD)
LOG(logDEBUG1, (" Reading Pattern Word (addr:0x%x)\n", addr));
// the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2;
@@ -182,7 +161,7 @@ void writePatternWord(int addr, uint64_t word) {
LOG(logDEBUG1, ("Setting Pattern Word (addr:0x%x, word:0x%llx)\n", addr,
(long long int)word));
#ifndef MYTHEN3D
#ifdef CHIPTESTBOARDD
uint32_t reg = PATTERN_CNTRL_REG;
// write word
@@ -199,7 +178,6 @@ void writePatternWord(int addr, uint64_t word) {
#ifdef VIRTUAL
virtual_pattern[addr] = word;
#endif
// mythen
#else
// the first word in RAM as base plus the offset of the word to write (addr)
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2;
@@ -223,29 +201,15 @@ int validate_getPatternWaitAddresses(char *message, int level, int *addr) {
}
int getPatternWaitAddress(int level) {
switch (level) {
case 0:
return ((bus_r(PATTERN_WAIT_0_ADDR_REG) & PATTERN_WAIT_0_ADDR_MSK) >>
PATTERN_WAIT_0_ADDR_OFST);
case 1:
return ((bus_r(PATTERN_WAIT_1_ADDR_REG) & PATTERN_WAIT_1_ADDR_MSK) >>
PATTERN_WAIT_1_ADDR_OFST);
case 2:
return ((bus_r(PATTERN_WAIT_2_ADDR_REG) & PATTERN_WAIT_2_ADDR_MSK) >>
PATTERN_WAIT_2_ADDR_OFST);
#ifndef MYTHEN3D
case 3:
return ((bus_r(PATTERN_WAIT_3_ADDR_REG) & PATTERN_WAIT_3_ADDR_MSK) >>
PATTERN_WAIT_3_ADDR_OFST);
case 4:
return ((bus_r(PATTERN_WAIT_4_ADDR_REG) & PATTERN_WAIT_4_ADDR_MSK) >>
PATTERN_WAIT_4_ADDR_OFST);
case 5:
return ((bus_r(PATTERN_WAIT_5_ADDR_REG) & PATTERN_WAIT_5_ADDR_MSK) >>
PATTERN_WAIT_5_ADDR_OFST);
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return -1;
} else {
return ((bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_WAIT_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET) &
PATTERN_WAIT_ADDR_MSK) >>
PATTERN_WAIT_ADDR_OFST);
}
}
@@ -289,35 +253,13 @@ void setPatternWaitAddress(int level, int addr) {
LOG(logINFO,
#endif
("Setting Pattern Wait Address (level:%d, addr:0x%x)\n", level, addr));
switch (level) {
case 0:
bus_w(PATTERN_WAIT_0_ADDR_REG,
((addr << PATTERN_WAIT_0_ADDR_OFST) & PATTERN_WAIT_0_ADDR_MSK));
break;
case 1:
bus_w(PATTERN_WAIT_1_ADDR_REG,
((addr << PATTERN_WAIT_1_ADDR_OFST) & PATTERN_WAIT_1_ADDR_MSK));
break;
case 2:
bus_w(PATTERN_WAIT_2_ADDR_REG,
((addr << PATTERN_WAIT_2_ADDR_OFST) & PATTERN_WAIT_2_ADDR_MSK));
break;
#ifndef MYTHEN3D
case 3:
bus_w(PATTERN_WAIT_3_ADDR_REG,
((addr << PATTERN_WAIT_3_ADDR_OFST) & PATTERN_WAIT_3_ADDR_MSK));
break;
case 4:
bus_w(PATTERN_WAIT_4_ADDR_REG,
((addr << PATTERN_WAIT_4_ADDR_OFST) & PATTERN_WAIT_4_ADDR_MSK));
break;
case 5:
bus_w(PATTERN_WAIT_5_ADDR_REG,
((addr << PATTERN_WAIT_5_ADDR_OFST) & PATTERN_WAIT_5_ADDR_MSK));
break;
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return;
} else {
bus_w(PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
((addr << PATTERN_WAIT_ADDR_OFST) & PATTERN_WAIT_ADDR_MSK));
}
}
@@ -340,39 +282,24 @@ int validate_getPatternWaitClocksAndInterval(char *message, int level,
}
uint64_t getPatternWaitClocks(int level) {
switch (level) {
case 0:
return getU64BitReg(PATTERN_WAIT_TIMER_0_LSB_REG,
PATTERN_WAIT_TIMER_0_MSB_REG);
case 1:
return getU64BitReg(PATTERN_WAIT_TIMER_1_LSB_REG,
PATTERN_WAIT_TIMER_1_MSB_REG);
case 2:
return getU64BitReg(PATTERN_WAIT_TIMER_2_LSB_REG,
PATTERN_WAIT_TIMER_2_MSB_REG);
#ifndef MYTHEN3D
case 3:
return getU64BitReg(PATTERN_WAIT_TIMER_3_LSB_REG,
PATTERN_WAIT_TIMER_3_MSB_REG);
case 4:
return getU64BitReg(PATTERN_WAIT_TIMER_4_LSB_REG,
PATTERN_WAIT_TIMER_4_MSB_REG);
case 5:
return getU64BitReg(PATTERN_WAIT_TIMER_5_LSB_REG,
PATTERN_WAIT_TIMER_5_MSB_REG);
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return -1;
} else {
return getU64BitReg(
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_LSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_MSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET);
}
}
uint64_t getPatternWaitInterval(int level) {
uint64_t numClocks = getPatternWaitClocks(level);
int runclk = 0;
#ifdef CHIPTESTBOARDD
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
runclk = clkFrequency[RUN_CLK];
#elif XILINX_CHIPTESTBOARDD
runclk = RUN_CLK;
#elif MYTHEN3D
runclk = clkDivider[SYSTEM_C0];
#endif
@@ -425,35 +352,18 @@ void setPatternWaitClocks(int level, uint64_t t) {
#endif
("Setting Pattern Wait Time in clocks (level:%d) :%lld\n", level,
(long long int)t));
switch (level) {
case 0:
setU64BitReg(t, PATTERN_WAIT_TIMER_0_LSB_REG,
PATTERN_WAIT_TIMER_0_MSB_REG);
break;
case 1:
setU64BitReg(t, PATTERN_WAIT_TIMER_1_LSB_REG,
PATTERN_WAIT_TIMER_1_MSB_REG);
break;
case 2:
setU64BitReg(t, PATTERN_WAIT_TIMER_2_LSB_REG,
PATTERN_WAIT_TIMER_2_MSB_REG);
break;
#ifndef MYTHEN3D
case 3:
setU64BitReg(t, PATTERN_WAIT_TIMER_3_LSB_REG,
PATTERN_WAIT_TIMER_3_MSB_REG);
break;
case 4:
setU64BitReg(t, PATTERN_WAIT_TIMER_4_LSB_REG,
PATTERN_WAIT_TIMER_4_MSB_REG);
break;
case 5:
setU64BitReg(t, PATTERN_WAIT_TIMER_5_LSB_REG,
PATTERN_WAIT_TIMER_5_MSB_REG);
break;
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return;
} else {
return setU64BitReg(
t,
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_LSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
PATTERN_LOOPDEF_BASE + (PATTERN_WAIT_TIMER_MSB_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET);
}
}
@@ -466,12 +376,10 @@ void setPatternWaitInterval(int level, uint64_t t) {
("Setting Pattern Wait Time (level:%d) :%lld ns\n", level,
(long long int)t));
int runclk = 0;
#ifdef CHIPTESTBOARDD
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
runclk = clkFrequency[RUN_CLK];
#elif XILINX_CHIPTESTBOARDD
runclk = RUN_CLK;
#elif MYTHEN3D
runclk = clkDivider[SYSTEM_C0];
runclk = clkDivider[SYSTEM_C0];
#endif
uint64_t numClocks = t * (1E-3 * runclk);
setPatternWaitClocks(level, numClocks);
@@ -491,23 +399,13 @@ int validate_getPatternLoopCycles(char *message, int level, int *numLoops) {
}
int getPatternLoopCycles(int level) {
switch (level) {
case 0:
return bus_r(PATTERN_LOOP_0_ITERATION_REG);
case 1:
return bus_r(PATTERN_LOOP_1_ITERATION_REG);
case 2:
return bus_r(PATTERN_LOOP_2_ITERATION_REG);
#ifndef MYTHEN3D
case 3:
return bus_r(PATTERN_LOOP_3_ITERATION_REG);
case 4:
return bus_r(PATTERN_LOOP_4_ITERATION_REG);
case 5:
return bus_r(PATTERN_LOOP_5_ITERATION_REG);
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return -1;
} else {
return bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_LOOP_ITERATION_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET);
}
}
@@ -546,29 +444,13 @@ void setPatternLoopCycles(int level, int nLoop) {
LOG(logINFO,
#endif
("Setting Pattern Loop Cycles(level:%d, nLoop:%d)\n", level, nLoop));
switch (level) {
case 0:
bus_w(PATTERN_LOOP_0_ITERATION_REG, nLoop);
break;
case 1:
bus_w(PATTERN_LOOP_1_ITERATION_REG, nLoop);
break;
case 2:
bus_w(PATTERN_LOOP_2_ITERATION_REG, nLoop);
break;
#ifndef MYTHEN3D
case 3:
bus_w(PATTERN_LOOP_3_ITERATION_REG, nLoop);
break;
case 4:
bus_w(PATTERN_LOOP_4_ITERATION_REG, nLoop);
break;
case 5:
bus_w(PATTERN_LOOP_5_ITERATION_REG, nLoop);
break;
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return;
} else {
bus_w(PATTERN_LOOPDEF_BASE + (PATTERN_LOOP_ITERATION_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
nLoop);
}
}
@@ -639,59 +521,22 @@ int validate_getPatternLoopAddresses(char *message, int level, int *startAddr,
}
void getPatternLoopAddresses(int level, int *startAddr, int *stopAddr) {
switch (level) {
case 0:
*startAddr =
((bus_r(PATTERN_LOOP_0_ADDR_REG) & PATTERN_LOOP_0_ADDR_STRT_MSK) >>
PATTERN_LOOP_0_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_0_ADDR_REG) & PATTERN_LOOP_0_ADDR_STP_MSK) >>
PATTERN_LOOP_0_ADDR_STP_OFST);
break;
case 1:
*startAddr =
((bus_r(PATTERN_LOOP_1_ADDR_REG) & PATTERN_LOOP_1_ADDR_STRT_MSK) >>
PATTERN_LOOP_1_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_1_ADDR_REG) & PATTERN_LOOP_1_ADDR_STP_MSK) >>
PATTERN_LOOP_1_ADDR_STP_OFST);
break;
case 2:
*startAddr =
((bus_r(PATTERN_LOOP_2_ADDR_REG) & PATTERN_LOOP_2_ADDR_STRT_MSK) >>
PATTERN_LOOP_2_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_2_ADDR_REG) & PATTERN_LOOP_2_ADDR_STP_MSK) >>
PATTERN_LOOP_2_ADDR_STP_OFST);
break;
#ifndef MYTHEN3D
case 3:
*startAddr =
((bus_r(PATTERN_LOOP_3_ADDR_REG) & PATTERN_LOOP_3_ADDR_STRT_MSK) >>
PATTERN_LOOP_3_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_3_ADDR_REG) & PATTERN_LOOP_3_ADDR_STP_MSK) >>
PATTERN_LOOP_3_ADDR_STP_OFST);
break;
case 4:
*startAddr =
((bus_r(PATTERN_LOOP_4_ADDR_REG) & PATTERN_LOOP_4_ADDR_STRT_MSK) >>
PATTERN_LOOP_4_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_4_ADDR_REG) & PATTERN_LOOP_4_ADDR_STP_MSK) >>
PATTERN_LOOP_4_ADDR_STP_OFST);
break;
case 5:
*startAddr =
((bus_r(PATTERN_LOOP_5_ADDR_REG) & PATTERN_LOOP_5_ADDR_STRT_MSK) >>
PATTERN_LOOP_5_ADDR_STRT_OFST);
*stopAddr =
((bus_r(PATTERN_LOOP_5_ADDR_REG) & PATTERN_LOOP_5_ADDR_STP_MSK) >>
PATTERN_LOOP_5_ADDR_STP_OFST);
break;
#endif
default:
return;
if (level < 0 || level >= MAX_LEVELS) {
*startAddr = -1;
*stopAddr = -1;
} else {
*startAddr = ((bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_LOOP_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET) &
PATTERN_LOOP_ADDR_STRT_MSK) >>
PATTERN_LOOP_ADDR_STRT_OFST);
*stopAddr = ((bus_r(PATTERN_LOOPDEF_BASE +
(PATTERN_LOOP_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET) &
PATTERN_LOOP_ADDR_STP_MSK) >>
PATTERN_LOOP_ADDR_STP_OFST);
}
}
@@ -747,53 +592,16 @@ void setPatternLoopAddresses(int level, int startAddr, int stopAddr) {
("Setting Pattern Loop Address (level:%d, startaddr:0x%x, "
"stopaddr:0x%x)\n",
level, startAddr, stopAddr));
switch (level) {
case 0:
bus_w(PATTERN_LOOP_0_ADDR_REG,
((startAddr << PATTERN_LOOP_0_ADDR_STRT_OFST) &
PATTERN_LOOP_0_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_0_ADDR_STP_OFST) &
PATTERN_LOOP_0_ADDR_STP_MSK));
break;
case 1:
bus_w(PATTERN_LOOP_1_ADDR_REG,
((startAddr << PATTERN_LOOP_1_ADDR_STRT_OFST) &
PATTERN_LOOP_1_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_1_ADDR_STP_OFST) &
PATTERN_LOOP_1_ADDR_STP_MSK));
break;
case 2:
bus_w(PATTERN_LOOP_2_ADDR_REG,
((startAddr << PATTERN_LOOP_2_ADDR_STRT_OFST) &
PATTERN_LOOP_2_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_2_ADDR_STP_OFST) &
PATTERN_LOOP_2_ADDR_STP_MSK));
break;
#ifndef MYTHEN3D
case 3:
bus_w(PATTERN_LOOP_3_ADDR_REG,
((startAddr << PATTERN_LOOP_3_ADDR_STRT_OFST) &
PATTERN_LOOP_3_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_3_ADDR_STP_OFST) &
PATTERN_LOOP_3_ADDR_STP_MSK));
break;
case 4:
bus_w(PATTERN_LOOP_4_ADDR_REG,
((startAddr << PATTERN_LOOP_4_ADDR_STRT_OFST) &
PATTERN_LOOP_4_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_4_ADDR_STP_OFST) &
PATTERN_LOOP_4_ADDR_STP_MSK));
break;
case 5:
bus_w(PATTERN_LOOP_5_ADDR_REG,
((startAddr << PATTERN_LOOP_5_ADDR_STRT_OFST) &
PATTERN_LOOP_5_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_5_ADDR_STP_OFST) &
PATTERN_LOOP_5_ADDR_STP_MSK));
break;
#endif
default:
if (level < 0 || level >= MAX_LEVELS) {
return;
} else {
bus_w(PATTERN_LOOPDEF_BASE + (PATTERN_LOOP_ADDR_WORD_OFST +
level * PATTERN_LOOPDEF_NWORDS_OFST) *
REG_OFFSET,
((startAddr << PATTERN_LOOP_ADDR_STRT_OFST) &
PATTERN_LOOP_ADDR_STRT_MSK) |
((stopAddr << PATTERN_LOOP_ADDR_STP_OFST) &
PATTERN_LOOP_ADDR_STP_MSK));
}
}
@@ -826,6 +634,17 @@ void startPattern() {
LOG(logINFOBLUE, ("Pattern done\n"));
}
#endif
#ifdef XILINX_CHIPTESTBOARDD
void startPattern() {
LOG(logINFOBLUE, ("Starting Pattern\n"));
bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
usleep(1);
while (bus_r(FLOW_CONTROL_REG) & RSM_BUSY_MSK) {
usleep(1);
}
LOG(logINFOBLUE, ("Pattern done\n"));
}
#endif
char *getPatternFileName() { return clientPatternfile; }

15
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
View File

@@ -5798,7 +5798,7 @@ int set_clock_frequency(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Setting clock (%d) frequency : %u\n", args[0], args[1]));
#if !defined(CHIPTESTBOARDD)
#if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -5811,7 +5811,7 @@ int set_clock_frequency(int file_des) {
case ADC_CLOCK:
c = ADC_CLK;
break;
#ifdef CHIPTESTBOARDD
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
case DBIT_CLOCK:
c = DBIT_CLK;
break;
@@ -5843,7 +5843,11 @@ int set_clock_frequency(int file_des) {
int retval = getFrequency(c);
LOG(logDEBUG1, ("retval %s: %d %s\n", modeName, retval,
myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
#if !defined( \
XILINX_CHIPTESTBOARDD) // XCTB will give the actual frequency, which is not
// 100% identical to the set frequency
validate(&ret, mess, val, retval, modeName, DEC);
#endif
}
}
}
@@ -5861,13 +5865,14 @@ int get_clock_frequency(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Getting clock (%d) frequency\n", arg));
#if !defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D)
#if !defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = 0;
switch (arg) {
#if defined(CHIPTESTBOARDD)
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
case ADC_CLOCK:
c = ADC_CLK;
break;
@@ -7463,7 +7468,7 @@ int start_pattern(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Starting Pattern\n"));
#ifndef MYTHEN3D
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
// only set

1
slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt
View File

@@ -6,6 +6,7 @@ add_executable(xilinx_ctbDetectorServer_virtual
../slsDetectorServer/src/slsDetectorServer_funcs.c
../slsDetectorServer/src/communication_funcs.c
../slsDetectorServer/src/arm64.c
../slsDetectorServer/src/XILINX_PLL.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/sharedMemory.c
../slsDetectorServer/src/loadPattern.c

2
slsDetectorServers/xilinx_ctbDetectorServer/Makefile
View File

@@ -23,7 +23,7 @@ DESTDIR ?= bin
INSTMODE = 0777
SRCS = slsDetectorFunctionList.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)XILINX_PLL.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
OBJS = $(SRCS:.c=.o)

516
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
View File

@@ -2,10 +2,16 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
// clang-format off
#define REG_OFFSET (4)
#define PATTERN_STEP0_MSB_REG (0x10004)
#define PATTERN_STEP0_LSB_REG (0x10000)
#define CTRL_REG (0x8000)
#define POWER_VIO_OFST (0)
#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
#define POWER_VIO_OFST (0)
#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
#define POWER_VCC_A_OFST (1)
#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
#define POWER_VCC_B_OFST (2)
@@ -17,20 +23,20 @@
#define STATUS_REG (0x8004)
#define PATTERN_RUNNING_OFST (0)
#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
#define RX_BUSY_OFST (1)
#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
#define PROCESSING_BUSY_OFST (2)
#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
#define UDP_GEN_BUSY_OFST (3)
#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
#define NETWORK_BUSY_OFST (4)
#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
#define PATTERN_RUNNING_OFST (0)
#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
#define RX_BUSY_OFST (1)
#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
#define PROCESSING_BUSY_OFST (2)
#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
#define UDP_GEN_BUSY_OFST (3)
#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
#define NETWORK_BUSY_OFST (4)
#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
#define WAIT_FOR_TRIGGER_OFST (5)
#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST)
#define RX_NOT_GOOD_OFST (6)
#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
#define RX_NOT_GOOD_OFST (6)
#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
#define STATUS_REG2 (0x8008)
@@ -38,8 +44,8 @@
#define FPGACOMPDATE_OFST (0)
#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define FPGA_GIT_HEAD (0x8010)
@@ -50,8 +56,8 @@
#define APICOMPDATE_OFST (0)
#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
#define APIDETTYPE_OFST (24)
#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
#define APIDETTYPE_OFST (24)
#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
#define A_FIFO_OVERFLOW_STATUS_REG (0x9000)
@@ -103,23 +109,22 @@
#define FIFO_TO_GB_CONTROL_REG (0xA000)
#define ENABLED_CHANNELS_ADC_OFST (0)
#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
#define ENABLED_CHANNELS_D_OFST (8)
#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
#define ENABLED_CHANNELS_X_OFST (9)
#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
#define RO_MODE_ADC_OFST (13)
#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
#define RO_MODE_D_OFST (14)
#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
#define RO_MODE_X_OFST (15)
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
#define ENABLED_CHANNELS_ADC_OFST (0)
#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
#define ENABLED_CHANNELS_D_OFST (8)
#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
#define ENABLED_CHANNELS_X_OFST (9)
#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
#define RO_MODE_ADC_OFST (13)
#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
#define RO_MODE_D_OFST (14)
#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
#define RO_MODE_X_OFST (15)
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
#define COUNT_FRAMES_FROM_UPDATE_MSK \
(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define START_STREAMING_P_OFST (17)
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define START_STREAMING_P_OFST (17)
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
#define STREAM_BUFFER_CLEAR_OFST (18)
#define STREAM_BUFFER_CLEAR_MSK (0x00000001 << STREAM_BUFFER_CLEAR_OFST)
@@ -148,26 +153,26 @@
#define PKTPACKETLENGTHREG (0xA020)
#define PACKETLENGTH1G_OFST (0)
#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
#define PACKETLENGTH1G_OFST (0)
#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
#define PACKETLENGTH10G_OFST (16)
#define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST)
#define PKTNOPACKETSREG (0xA024)
#define NOPACKETS1G_OFST (0)
#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
#define NOPACKETS1G_OFST (0)
#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
#define NOPACKETS10G_OFST (16)
#define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST)
#define PKTCTRLREG (0xA028)
#define NOSERVERS_OFST (0)
#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
#define NOSERVERS_OFST (0)
#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
#define SERVERSTART_OFST (8)
#define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST)
#define ETHINTERF_OFST (16)
#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
#define ETHINTERF_OFST (16)
#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
#define PKTCOORDREG1 (0xA02C)
@@ -181,363 +186,282 @@
#define COORDZ_OFST (0)
#define COORDZ_MSK (0x0000ffff << COORDZ_OFST)
#define FLOW_STATUS_REG (0xB000)
#define PATTERN_OUT_LSB_REG (0xB000)
#define RSM_BUSY_OFST (0)
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
#define RSM_TRG_WAIT_OFST (3)
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
#define CSM_BUSY_OFST (17)
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
#define PATTERN_OUT_MSB_REG (0xB004)
#define FLOW_CONTROL_REG (0xB004)
#define PATTERN_IN_LSB_REG (0xB008)
#define START_F_OFST (0)
#define START_F_MSK (0x00000001 << START_F_OFST)
#define STOP_F_OFST (1)
#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
#define RST_F_OFST (2)
#define RST_F_MSK (0x00000001 << RST_F_OFST)
#define SW_TRIGGER_F_OFST (3)
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
#define TRIGGER_ENABLE_OFST (4)
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
#define PATTERN_IN_MSB_REG (0xB00C)
#define TIME_FROM_START_OUT_REG_1 (0xB008)
#define PATTERN_MASK_LSB_REG (0xB010)
#define TIME_FROM_START_OUT_REG_2 (0xB00C)
#define PATTERN_MASK_MSB_REG (0xB014)
#define FRAMES_FROM_START_OUT_REG_1 (0xB010)
#define PATTERN_SET_LSB_REG (0xB018)
#define FRAMES_FROM_START_OUT_REG_2 (0xB014)
#define PATTERN_SET_MSB_REG (0xB01C)
#define FRAME_TIME_OUT_REG_1 (0xB018)
#define PATTERN_CNTRL_REG (0xB020)
#define FRAME_TIME_OUT_REG_2 (0xB01C)
#define DELAY_OUT_REG_1 (0xB020)
#define DELAY_OUT_REG_2 (0xB024)
#define CYCLES_OUT_REG_1 (0xB028)
#define CYCLES_OUT_REG_2 (0xB02C)
#define FRAMES_OUT_REG_1 (0xB030)
#define FRAMES_OUT_REG_2 (0xB034)
#define PERIOD_OUT_REG_1 (0xB038)
#define PERIOD_OUT_REG_2 (0xB03C)
#define DELAY_IN_REG_1 (0xB040)
#define DELAY_IN_REG_2 (0xB044)
#define CYCLES_IN_REG_1 (0xB048)
#define CYCLES_IN_REG_2 (0xB04C)
#define FRAMES_IN_REG_1 (0xB050)
#define FRAMES_IN_REG_2 (0xB054)
#define PERIOD_IN_REG_1 (0xB058)
#define PERIOD_IN_REG_2 (0xB05C)
#define PATTERN_OUT_LSB_REG (0xB100)
#define PATTERN_OUT_MSB_REG (0xB104)
#define PATTERN_IN_LSB_REG (0xB108)
#define PATTERN_IN_MSB_REG (0xB10C)
#define PATTERN_MASK_LSB_REG (0xB110)
#define PATTERN_MASK_MSB_REG (0xB114)
#define PATTERN_SET_LSB_REG (0xB118)
#define PATTERN_SET_MSB_REG (0xB11C)
#define PATTERN_CNTRL_REG (0xB120)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
#define PATTERN_LIMIT_REG (0xB124)
#define PATTERN_LIMIT_REG (0xB024)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LOOP_0_ADDR_REG (0xB128)
#define PATTERN_IO_CNTRL_LSB_REG (0xB028)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
#define PATTERN_IO_CNTRL_MSB_REG (0xB02C)
#define PATTERN_LOOP_0_ITERATION_REG (0xB12C)
#define FLOW_CONTROL_REG (0xB030)
#define PATTERN_WAIT_0_ADDR_REG (0xB130)
#define START_F_OFST (0)
#define START_F_MSK (0x00000001 << START_F_OFST)
#define STOP_F_OFST (1)
#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
#define RST_F_OFST (2)
#define RST_F_MSK (0x00000001 << RST_F_OFST)
#define SW_TRIGGER_F_OFST (3)
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
#define TRIGGER_ENABLE_OFST (4)
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
#define RSM_BUSY_OFST (5)
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
#define RSM_TRG_WAIT_OFST (6)
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
#define CSM_BUSY_OFST (7)
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
#define DELAY_IN_REG_1 (0xB034)
#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB134)
#define DELAY_IN_REG_2 (0xB038)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB138)
#define CYCLES_IN_REG_1 (0xB03C)
#define PATTERN_LOOP_1_ADDR_REG (0xB13C)
#define CYCLES_IN_REG_2 (0xB040)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
#define FRAMES_IN_REG_1 (0xB044)
#define PATTERN_LOOP_1_ITERATION_REG (0xB140)
#define FRAMES_IN_REG_2 (0xB048)
#define PATTERN_WAIT_1_ADDR_REG (0xB144)
#define PERIOD_IN_REG_1 (0xB04C)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
#define PERIOD_IN_REG_2 (0xB050)
#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB148)
#define PATTERN_TEST_REG (0xB054)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB14C)
#define PATTERN_FIRMWARE_REG (0xB058)
#define PATTERN_LOOP_2_ADDR_REG (0xB150)
#define PATTERN_WIDTH_OFST (0)
#define PATTERN_WIDTH_MSK (0x000000ff << PATTERN_WIDTH_OFST)
#define PATTERN_ADDR_WIDTH_OFST (8)
#define PATTERN_ADDR_WIDTH_MSK (0x000000ff << PATTERN_ADDR_WIDTH_OFST)
#define PATTERN_NLOOPS_NWAITS_OFST (16)
#define PATTERN_NLOOPS_NWAITS_MSK (0x000000ff << PATTERN_NLOOPS_NWAITS_OFST)
#define DIRECT_PATTERN_RAM_OFST (24)
#define DIRECT_PATTERN_RAM_MSK (0x00000001 << DIRECT_PATTERN_RAM_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
#define TIME_FROM_START_OUT_REG_1 (0xB05C)
#define PATTERN_LOOP_2_ITERATION_REG (0xB154)
#define TIME_FROM_START_OUT_REG_2 (0xB060)
#define PATTERN_WAIT_2_ADDR_REG (0xB158)
#define FRAMES_FROM_START_OUT_REG_1 (0xB064)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
#define FRAMES_FROM_START_OUT_REG_2 (0xB068)
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB15C)
#define FRAME_TIME_OUT_REG_1 (0xB06C)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB160)
#define FRAME_TIME_OUT_REG_2 (0xB070)
#define PATTERN_LOOP_3_ADDR_REG (0xB164)
#define PATTERN_LOOPDEF_BASE (0xB080)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
#define PATTERN_LOOP_ADDR_WORD_OFST (0)
#define PATTERN_LOOP_ADDR_WORD_MSK (0x00000001 << PATTERN_LOOP_ADDR_WORD_OFST)
#define PATTERN_LOOP_ITERATION_WORD_OFST (1)
#define PATTERN_LOOP_ITERATION_WORD_MSK (0x00000001 << PATTERN_LOOP_ITERATION_WORD_OFST)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_WAIT_ADDR_WORD_MSK (0x00000001 << PATTERN_WAIT_ADDR_WORD_OFST)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3)
#define PATTERN_WAIT_TIMER_LSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_LSB_WORD_OFST)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4)
#define PATTERN_WAIT_TIMER_MSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_MSB_WORD_OFST)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
#define PATTERN_LOOPDEF_NWORDS_MSK (0x00000001 << PATTERN_LOOPDEF_NWORDS_OFST)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001fff << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_ADDR_STP_OFST)
#define PATTERN_LOOP_3_ITERATION_REG (0xB168)
#define DBITFIFOCTRLREG (0xC000)
#define PATTERN_WAIT_3_ADDR_REG (0xB16C)
#define PATTERN_WAIT_3_ADDR_OFST (0)
#define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB170)
#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB174)
#define PATTERN_LOOP_4_ADDR_REG (0xB178)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
#define PATTERN_LOOP_4_ITERATION_REG (0xB17C)
#define PATTERN_WAIT_4_ADDR_REG (0xB180)
#define PATTERN_WAIT_4_ADDR_OFST (0)
#define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB184)
#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB188)
#define PATTERN_LOOP_5_ADDR_REG (0xB18C)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
#define PATTERN_LOOP_5_ITERATION_REG (0xB190)
#define PATTERN_WAIT_5_ADDR_REG (0xB194)
#define PATTERN_WAIT_5_ADDR_OFST (0)
#define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB198)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB19C)
#define PINIOCTRLREG (0xB1A0)
#define DBITFIFOCTRLREG (0xB1A4)
#define DBITRD_OFST (0)
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
#define DBITRST_OFST (1)
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
#define DBITFULL_OFST (2)
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
#define DBITEMPTY_OFST (3)
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
#define DBITRD_OFST (0)
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
#define DBITRST_OFST (1)
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
#define DBITFULL_OFST (2)
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
#define DBITEMPTY_OFST (3)
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
#define DBITUNDERFLOW_OFST (4)
#define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST)
#define DBITOVERFLOW_OFST (5)
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
#define DBITOVERFLOW_OFST (5)
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
#define DBITFIFODATAREG1 (0xB1A8)
#define DBITFIFODATAREG1 (0xC004)
#define DBITFIFODATAREG2 (0xB1AC)
#define DBITFIFODATAREG2 (0xC008)
#define MATTERHORNSPIREG1 (0xB1B0)
#define MATTERHORNSPIREG1 (0xC00C)
#define MATTERHORNSPIREG2 (0xB1B4)
#define MATTERHORNSPIREG2 (0xC010)
#define MATTERHORNSPICTRL (0xB1B8)
#define MATTERHORNSPICTRL (0xC014)
#define CONFIGSTART_P_OFST (0)
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
#define PERIPHERYRST_P_OFST (1)
#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
#define STARTREAD_P_OFST (2)
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
#define BUSY_OFST (3)
#define BUSY_MSK (0x00000001 << BUSY_OFST)
#define CONFIGSTART_P_OFST (0)
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
#define PERIPHERYRST_P_OFST (1)
#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
#define STARTREAD_P_OFST (2)
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
#define BUSY_OFST (3)
#define BUSY_MSK (0x00000001 << BUSY_OFST)
#define READOUTFROMASIC_OFST (4)
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
#define TRANSCEIVERRXCTRL0REG1 (0xB800)
#define TRANSCEIVERRXCTRL0REG1 (0xC100)
#define TRANSCEIVERRXCTRL0REG2 (0xB804)
#define TRANSCEIVERRXCTRL0REG2 (0xC104)
#define TRANSCEIVERRXCTRL1REG1 (0xB808)
#define TRANSCEIVERRXCTRL1REG1 (0xC108)
#define TRANSCEIVERRXCTRL1REG2 (0xB80C)
#define TRANSCEIVERRXCTRL1REG2 (0xC10C)
#define TRANSCEIVERRXCTRL2REG (0xB810)
#define TRANSCEIVERRXCTRL2REG (0xC110)
#define TRANSCEIVERRXCTRL3REG (0xB814)
#define TRANSCEIVERRXCTRL3REG (0xC114)
#define TRANSCEIVERSTATUS (0xB818)
#define TRANSCEIVERSTATUS (0xC118)
#define LINKDOWNLATCHEDOUT_OFST (0)
#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
#define TXUSERCLKACTIVE_OFST (1)
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
#define RXUSERCLKACTIVE_OFST (2)
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
#define RXCOMMADET_OFST (3)
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
#define RXBYTEREALIGN_OFST (7)
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
#define RXBYTEISALIGNED_OFST (11)
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
#define GTWIZRXCDRSTABLE_OFST (15)
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
#define RESETTXDONE_OFST (16)
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
#define RESETRXDONE_OFST (17)
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
#define RXPMARESETDONE_OFST (18)
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
#define TXPMARESETDONE_OFST (22)
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
#define GTTPOWERGOOD_OFST (26)
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
#define TXUSERCLKACTIVE_OFST (1)
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
#define RXUSERCLKACTIVE_OFST (2)
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
#define RXCOMMADET_OFST (3)
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
#define RXBYTEREALIGN_OFST (7)
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
#define RXBYTEISALIGNED_OFST (11)
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
#define GTWIZRXCDRSTABLE_OFST (15)
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
#define RESETTXDONE_OFST (16)
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
#define RESETRXDONE_OFST (17)
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
#define RXPMARESETDONE_OFST (18)
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
#define TXPMARESETDONE_OFST (22)
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
#define GTTPOWERGOOD_OFST (26)
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
#define TRANSCEIVERSTATUS2 (0xB81C)
#define TRANSCEIVERSTATUS2 (0xC11C)
#define RXLOCKED_OFST (0)
#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
#define TRANSCEIVERCONTROL (0xB820)
#define TRANSCEIVERCONTROL (0xC120)
#define GTWIZRESETALL_OFST (0)
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
#define GTWIZRESETALL_OFST (0)
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
#define RESETTXPLLANDDATAPATH_OFST (1)
#define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
#define RESETTXDATAPATHIN_OFST (2)
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
#define RESETTXDATAPATHIN_OFST (2)
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
#define RESETRXPLLANDDATAPATH_OFST (3)
#define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
#define RESETRXDATAPATHIN_OFST (4)
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
#define RXPOLARITY_OFST (5)
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
#define RXERRORCNTRESET_OFST (9)
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define RESETRXDATAPATHIN_OFST (4)
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
#define RXPOLARITY_OFST (5)
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
#define RXERRORCNTRESET_OFST (9)
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define TRANSCEIVERERRCNT_REG0 (0xB824)
#define TRANSCEIVERERRCNT_REG0 (0xC124)
#define TRANSCEIVERERRCNT_REG1 (0xB828)
#define TRANSCEIVERERRCNT_REG1 (0xC128)
#define TRANSCEIVERERRCNT_REG2 (0xB82C)
#define TRANSCEIVERERRCNT_REG2 (0xC12C)
#define TRANSCEIVERERRCNT_REG3 (0xB830)
#define TRANSCEIVERERRCNT_REG3 (0xC130)
#define TRANSCEIVERALIGNCNT_REG0 (0xB834)
#define TRANSCEIVERALIGNCNT_REG0 (0xC134)
#define RXALIGNCNTCH0_OFST (0)
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
#define TRANSCEIVERALIGNCNT_REG1 (0xB838)
#define TRANSCEIVERALIGNCNT_REG1 (0xC138)
#define RXALIGNCNTCH1_OFST (0)
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
#define TRANSCEIVERALIGNCNT_REG2 (0xB83C)
#define TRANSCEIVERALIGNCNT_REG2 (0xC13C)
#define RXALIGNCNTCH2_OFST (0)
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
#define TRANSCEIVERALIGNCNT_REG3 (0xB840)
#define TRANSCEIVERALIGNCNT_REG3 (0xC140)
#define RXALIGNCNTCH3_OFST (0)
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
#define TRANSCEIVERLASTWORD_REG0 (0xB844)
#define TRANSCEIVERLASTWORD_REG0 (0xC144)
#define RXDATACH0_OFST (0)
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
#define TRANSCEIVERLASTWORD_REG1 (0xB848)
#define TRANSCEIVERLASTWORD_REG1 (0xC148)
#define RXDATACH1_OFST (0)
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
#define TRANSCEIVERLASTWORD_REG2 (0xB84C)
#define TRANSCEIVERLASTWORD_REG2 (0xC14C)
#define RXDATACH2_OFST (0)
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
#define TRANSCEIVERLASTWORD_REG3 (0xB850)
#define TRANSCEIVERLASTWORD_REG3 (0xC150)
#define RXDATACH3_OFST (0)
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
// ----------------------------------------------------
// TODO: fix these in the firmware reg generator:
// ----------------------------------------------------:
#define DELAY_OUT_REG_1 (0xB054)
#define DELAY_OUT_REG_2 (0xB058)
#define CYCLES_OUT_REG_1 (0xB05C)
#define CYCLES_OUT_REG_2 (0xB060)
#define FRAMES_OUT_REG_1 (0xB064)
#define FRAMES_OUT_REG_2 (0xB068)
#define PERIOD_OUT_REG_1 (0xB06C)
#define PERIOD_OUT_REG_2 (0xB070)
// clang-format on

BIN
slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer
View File

Binary file not shown.

20
slsDetectorServers/xilinx_ctbDetectorServer/chip_config_xilinx.txt
View File

@@ -1,24 +1,24 @@
# Prepare MH02 configuration
reg 0xB1B0 0x00000041
reg 0xB1B4 0x01200004
reg 0xC00C 0x00000041
reg 0xC010 0x01200004
# configure Matterhorn SPI
setbit 0xB1B8 0
setbit 0xC014 0
# wait till config is done
pollbit 0xB1B8 3 0
pollbit 0xC014 3 0
# reset transceiver
reg 0xB820 0x0
reg 0xB820 0x1
reg 0xB820 0x0
reg 0xC120 0x0
reg 0xC120 0x1
reg 0xC120 0x0
# set MSB LSB inversions and polarity for transceiver
reg 0xB820 0x61e0
reg 0xC120 0x61e0
# Enable MH02 PLL clock
pattern enable_clock_pattern.pyat
# start the flow
setbit 0xB004 0
clearbit 0xB004 0
setbit 0xB030 0
clearbit 0xB030 0
sleep 1

24
slsDetectorServers/xilinx_ctbDetectorServer/reset_chip_xilinx.txt
View File

@@ -1,30 +1,30 @@
# turn off clock
setbit 0xB1B0 16
setbit 0xB1B8 0
setbit 0xC00C 16
setbit 0xC014 0
sleep 1
# reset Matterhorn periphery
setbit 0xB1B8 1
setbit 0xC014 1
sleep 1
# turn on clock
clearbit 0xB1B0 16
setbit 0xB1B8 0
clearbit 0xC00C 16
setbit 0xC014 0
sleep 1
# reset rx transceiver datapath
setbit 0xB820 4
setbit 0xC120 4
sleep 1
# reset 8b10b counters
setbit 0xB820 9
setbit 0xB820 10
setbit 0xB820 11
setbit 0xB820 12
setbit 0xC120 9
setbit 0xC120 10
setbit 0xC120 11
setbit 0xC120 12
sleep 1
clearbit 0xB820 9
clearbit 0xB820 10
clearbit 0xC120 9
clearbit 0xC120 10
# reset buffer fifos
reg 0x9024 0xFFFFFFFF

28
slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c
View File

@@ -9,6 +9,7 @@
#include "sls/versionAPI.h"
#include "LTC2620_Driver.h"
#include "XILINX_PLL.h"
#include "loadPattern.h"
#ifdef VIRTUAL
@@ -39,6 +40,8 @@ char initErrorMessage[MAX_STR_LENGTH];
int detPos[2] = {0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {20, 100, 20, 100};
int chipConfigured = 0;
int analogEnable = 0;
int digitalEnable = 0;
@@ -1778,3 +1781,28 @@ void getNumberOfChannels(int *nchanx, int *nchany) {
int getNumberOfChips() { return NCHIP; }
int getNumberOfDACs() { return NDAC; }
int getNumberOfChannelsPerChip() { return NCHAN; }
int setFrequency(enum CLKINDEX ind, int val) {
if (ind < 0 || ind >= NUM_CLOCKS) {
LOG(logERROR, ("Unknown clock index %d to set frequency\n", ind));
return FAIL;
}
if (val <= 0) {
return FAIL;
}
char *clock_names[] = {CLK_NAMES};
LOG(logINFO, ("\tSetting %s clock (%d) frequency to %d MHz\n",
clock_names[ind], ind, val));
XILINX_PLL_setFrequency(ind, val);
return OK;
}
int getFrequency(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind));
return -1;
}
return XILINX_PLL_getFrequency(ind);
}

7
slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorServer_defs.h
View File

@@ -72,10 +72,6 @@
#define VIO_MIN_MV (1200) // for fpga to function
#define TICK_CLK (20) // MHz (trig_timeFromStart, frametime, timeFromStart)
#define RUN_CLK \
(100) // MHz (framesFromStart, c_swTrigger, run, waitForTrigger, starting,
// acquiring, waitForPeriod, internalStop, c_framesFromSTart_reset,
// s_start, c_stop, triggerEnable, period, frames, cycles, delay)
/* Defines in the Firmware */
#define WAIT_TIME_PATTERN_READ (10)
@@ -158,3 +154,6 @@ typedef struct udp_header_struct {
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"