mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
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e7a91d38f2
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
12 lines
375 B
C
12 lines
375 B
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#include <stdbool.h>
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#include <stdint.h>
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void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq);
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uint32_t XILINX_PLL_getFrequency(uint32_t clkIDX);
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bool XILINX_PLL_isLocked();
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void XILINX_PLL_reset();
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void XILINX_PLL_waitForLock();
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void XILINX_PLL_load(); |