xilinx: using kHz, mult factor is 1E-6 converting ns to kHz (previously MHz->1E-6) (#1309)

slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h

@@ -54,6 +54,7 @@
 #define DEFAULT_ADC_CLK               (40)  // 20
 #define DEFAULT_SYNC_CLK              (40)  // 20
 #define DEFAULT_DBIT_CLK              (200)
+#define NS_TO_CLK_CYCLE               (1E-3) // ns to MHz
 #define DEFAULT_TRANSCEIVER_MASK      (0x3)
 
 #define MAX_TRANSCEIVER_MASK    (0xF)

slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h

@@ -63,6 +63,7 @@
 #define DEFAULT_SYSTEM_C1           (6)  //(166666666) // str_clk, 166 MHz const
 #define DEFAULT_SYSTEM_C2           (5)  //(200000000) // smp_clk, 200 MHz const
 #define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
+#define NS_TO_CLK_CYCLE             (1E-3) // ns to MHz
 
 #define FULL_SPEED_CLKDIV    (10) //(100000000) 100 MHz
 #define HALF_SPEED_CLKDIV    (20) //( 50000000) 50 MHz

slsDetectorServers/slsDetectorServer/src/loadPattern.c

@@ -307,7 +307,7 @@ uint64_t getPatternWaitInterval(int level) {
         LOG(logERROR, ("runclk is 0. Cannot divide by 0. Returning -1.\n"));
         return -1;
     }
-    return numClocks / (1E-3 * runclk);
+    return numClocks / (NS_TO_CLK_CYCLE * runclk);
 }
 
 int validate_setPatternWaitClocksAndInterval(char *message, int level,
@@ -381,7 +381,7 @@ void setPatternWaitInterval(int level, uint64_t t) {
 #elif MYTHEN3D
     runclk = clkDivider[SYSTEM_C0];
 #endif
-    uint64_t numClocks = t * (1E-3 * runclk);
+    uint64_t numClocks = t * (NS_TO_CLK_CYCLE * runclk);
     setPatternWaitClocks(level, numClocks);
 }
 

slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c

@@ -1064,12 +1064,12 @@ int setPeriod(int64_t val) {
         return FAIL;
     }
     LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
-    val *= (1E-3 * clkFrequency[RUN_CLK]);
+    val *= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
     setU64BitReg(val, PERIOD_IN_REG_1, PERIOD_IN_REG_2);
 
     // validate for tolerance
     int64_t retval = getPeriod();
-    val /= (1E-3 * clkFrequency[RUN_CLK]);
+    val /= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
     if (val != retval) {
         return FAIL;
     }
@@ -1078,7 +1078,7 @@ int setPeriod(int64_t val) {
 
 int64_t getPeriod() {
     return getU64BitReg(PERIOD_IN_REG_1, PERIOD_IN_REG_2) /
-           (1E-3 * clkFrequency[RUN_CLK]);
+           (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
 }
 
 int setDelayAfterTrigger(int64_t val) {
@@ -1087,12 +1087,12 @@ int setDelayAfterTrigger(int64_t val) {
         return FAIL;
     }
     LOG(logINFO, ("Setting delay after trigger %ld ns\n", val));
-    val *= (1E-3 * clkFrequency[RUN_CLK]);
+    val *= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
     setU64BitReg(val, DELAY_IN_REG_1, DELAY_IN_REG_2);
 
     // validate for tolerance
     int64_t retval = getDelayAfterTrigger();
-    val /= (1E-3 * clkFrequency[RUN_CLK]);
+    val /= (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
     if (val != retval) {
         return FAIL;
     }
@@ -1101,7 +1101,7 @@ int setDelayAfterTrigger(int64_t val) {
 
 int64_t getDelayAfterTrigger() {
     return getU64BitReg(DELAY_IN_REG_1, DELAY_IN_REG_2) /
-           (1E-3 * clkFrequency[RUN_CLK]);
+           (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
 }
 
 int64_t getNumFramesLeft() {
@@ -1114,12 +1114,12 @@ int64_t getNumTriggersLeft() {
 
 int64_t getDelayAfterTriggerLeft() {
     return getU64BitReg(DELAY_OUT_REG_1, DELAY_OUT_REG_2) /
-           (1E-3 * clkFrequency[RUN_CLK]);
+           (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
 }
 
 int64_t getPeriodLeft() {
     return getU64BitReg(PERIOD_OUT_REG_1, PERIOD_OUT_REG_2) /
-           (1E-3 * clkFrequency[RUN_CLK]);
+           (NS_TO_CLK_CYCLE * clkFrequency[RUN_CLK]);
 }
 
 int64_t getFramesFromStart() {
@@ -1129,12 +1129,12 @@ int64_t getFramesFromStart() {
 
 int64_t getActualTime() {
     return getU64BitReg(TIME_FROM_START_OUT_REG_1, TIME_FROM_START_OUT_REG_2) /
-           (1E-3 * clkFrequency[SYNC_CLK]);
+           (NS_TO_CLK_CYCLE * clkFrequency[SYNC_CLK]);
 }
 
 int64_t getMeasurementTime() {
     return getU64BitReg(FRAME_TIME_OUT_REG_1, FRAME_TIME_OUT_REG_2) /
-           (1E-3 * clkFrequency[SYNC_CLK]);
+           (NS_TO_CLK_CYCLE * clkFrequency[SYNC_CLK]);
 }
 
 /* parameters - dac, adc, hv */

slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorServer_defs.h

@@ -159,4 +159,5 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
 #define DEFAULT_RUN_CLK  (20000)  // 20 MHz
 #define DEFAULT_ADC_CLK  (100000) // 100 MHz
 #define DEFAULT_SYNC_CLK (20000)  // 20 MHz
-#define DEFAULT_DBIT_CLK (100000) // 100 MHz
+#define DEFAULT_DBIT_CLK (100000) // 100 MHz
+#define NS_TO_CLK_CYCLE  (1E-6)   // ns to kHz

slsSupportLib/include/sls/versionAPI.h

@@ -7,6 +7,6 @@
 #define APIGOTTHARD2 "0.0.0 0x250909"
 #define APIMOENCH    "0.0.0 0x250909"
 #define APIEIGER     "0.0.0 0x250909"
-#define APIXILINXCTB "0.0.0 0x250923"
+#define APIXILINXCTB "0.0.0 0x250924"
 #define APIJUNGFRAU  "0.0.0 0x250909"
 #define APIMYTHEN3   "0.0.0 0x250922"