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mx/Jungfraujoch
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Code Issues Pull Requests 1 Actions 1 Packages Projects Releases 55 Wiki Activity
204 Commits 73 Branches 140 Tags
5ec4d41e6892e8277c2acae1ef973aa0f271c5d0
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8 Commits

Author SHA1 Message Date
leonarski_f a3996a81e3 FPGA: Remove data collection counter 2023-05-30 20:13:54 +02:00
leonarski_f 72cdb88c0c FPGA: Add host_writer idle marker 2023-05-27 21:45:21 +02:00
leonarski_f 7c9a5238e2 FPGA: Minor improvements to data_collection_fsm 2023-05-27 18:39:35 +02:00
leonarski_f b926e69885 FPGA: data_collection_fsm counter 2023-05-26 20:39:12 +02:00
leonarski_f 8b87bb857b FPGA: clean-up unnecessary signals (from OC design) 2023-05-26 19:38:07 +02:00
leonarski_f 2dfd6e916d FPGA: work completion queue is extended to 32768 elements. 2023-05-24 11:57:56 +02:00
leonarski_f 97bf8f7e4a FPGA: Reduce UltraRAM FIFO (a bit) 2023-05-17 21:55:41 +02:00
leonarski_f 1757d42182 Initial commit
Signed-off-by: Filip Leonarski <filip.leonarski@psi.ch>
2023-04-06 11:17:59 +02:00
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