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FPGA: Remove data collection counter

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This commit is contained in:
leonarski_f
2023-05-30 20:13:54 +02:00
parent 8c1e55b6f3
commit a3996a81e3
15 changed files with 57 additions and 104 deletions
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1
grpc/jfjoch.proto
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@@ -380,7 +380,6 @@ message FPGAStatus {
uint32 error_eth = 38;
uint32 error_packet_len = 39;
uint32 data_collection_counter = 40;
bool host_writer_idle = 41;
}

2
image_analysis/fast-feedback-indexer

Submodule image_analysis/fast-feedback-indexer updated: 0db516f124...6eccc70b52

96
python/jfjoch_pb2.py
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File diff suppressed because one or more lines are too long

10
receiver/hdl/action_config.v
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@@ -15,7 +15,6 @@
`define ADDR_ACTION_TYPE 16'h0010
`define ADDR_RELEASE_LEVEL 16'h0014
`define ADDR_DATA_COLL_COUNTER 16'h0018
`define ADDR_MAX_MODULES_FPGA 16'h0020
`define ADDR_MODS_INT_PKT_GEN 16'h0024
@@ -93,8 +92,6 @@ module action_config
output reg data_collection_start ,
output reg data_collection_cancel ,
input data_collection_idle ,
input [0:31] data_collection_counter ,
input data_collection_counter_valid,
input host_writer_idle ,
input calib_data_fifo_empty ,
@@ -180,7 +177,6 @@ localparam
reg [63:0] reg_packets_udp;
reg [63:0] reg_packets_sls;
reg [31:0] reg_data_collection_counter;
reg [31:0] reg_udp_err_len;
reg [31:0] reg_udp_err_eth;
@@ -366,9 +362,6 @@ always @(posedge clk) begin
`ADDR_FIFO_STATUS: begin
rdata <= reg_fifo_status;
end
`ADDR_DATA_COLL_COUNTER: begin
rdata <= reg_data_collection_counter;
end
default:
rdata <= 32'hffffffff;
endcase
@@ -512,7 +505,6 @@ always @ (posedge clk) begin
reg_packets_icmp <= 0;
reg_packets_sls <= 0;
reg_host_writer_err <= 0;
reg_data_collection_counter <= 0;
end
else
begin
@@ -522,8 +514,6 @@ always @ (posedge clk) begin
reg_stalls_host <= stalls_host;
if (packets_processed_valid)
reg_packets_processed <= packets_processed;
if (data_collection_counter_valid)
reg_data_collection_counter <= data_collection_counter;
if (packets_eth_valid)
reg_packets_eth <= packets_eth;
if (packets_udp_valid)

7
receiver/hls/data_collection_fsm.cpp
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@@ -1,7 +1,6 @@
// Copyright (2019-2022) Paul Scherrer Institute
// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
#include <iostream>
#include "hls_jfjoch.h"
void data_collection_fsm(AXI_STREAM &eth_in,
@@ -11,7 +10,6 @@ void data_collection_fsm(AXI_STREAM &eth_in,
volatile ap_uint<1> &in_run,
volatile ap_uint<1> &in_cancel,
volatile ap_uint<1> &out_idle,
uint32_t &counter,
ap_uint<32> mode,
ap_uint<32> one_over_energy,
ap_uint<32> nframes,
@@ -26,7 +24,6 @@ void data_collection_fsm(AXI_STREAM &eth_in,
#pragma HLS INTERFACE ap_none register port=in_run
#pragma HLS INTERFACE ap_none register port=in_cancel
#pragma HLS INTERFACE ap_none register port=out_idle
#pragma HLS INTERFACE ap_vld register port=counter
#pragma HLS INTERFACE ap_none register port=mode
#pragma HLS INTERFACE ap_none register port=one_over_energy
@@ -43,7 +40,6 @@ void data_collection_fsm(AXI_STREAM &eth_in,
enum rcv_state_t {RCV_WAIT_FOR_START = 0, RCV_WAIT_FOR_START_LOW = 1, RCV_START = 2, RCV_INIT = 3, RCV_GOOD = 4,
RCV_FLUSH = 5, RCV_LAST = 6, RCV_FLUSH_IDLE = 7, RCV_IGNORE = 8};
static rcv_state_t rcv_state = RCV_WAIT_FOR_START;
static uint64_t internal_counter = 0;
#pragma HLS RESET variable=rcv_state
@@ -74,13 +70,11 @@ void data_collection_fsm(AXI_STREAM &eth_in,
case RCV_START:
out_idle = 0;
packet_out.data = 0;
internal_counter++;
ACT_REG_MODE(packet_out.data) = mode;
ACT_REG_ONE_OVER_ENERGY(packet_out.data) = one_over_energy;
ACT_REG_NFRAMES(packet_out.data) = nframes;
ACT_REG_NMODULES(packet_out.data) = nmodules;
ACT_REG_NSTORAGE_CELLS(packet_out.data) = nstorage_cells + 1;
ACT_REG_COUNTER(packet_out.data) = internal_counter;
packet_out.user = 0;
packet_out.last = 0;
@@ -150,6 +144,5 @@ void data_collection_fsm(AXI_STREAM &eth_in,
rcv_state = RCV_WAIT_FOR_START;
break;
}
counter = internal_counter;
}

2
receiver/hls/hls_jfjoch.h
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@@ -62,7 +62,6 @@ typedef hls::stream<packet_512_t> STREAM_512;
#define ACT_REG_MODE(x) ((x)(32 , 0)) // 32 bit
#define ACT_REG_ONE_OVER_ENERGY(x) ((x)(63 , 32)) // 32 bit
#define ACT_REG_NFRAMES(x) ((x)(95 , 64)) // 32 bit
#define ACT_REG_COUNTER(x) ((x)(127, 96)) // 32 bit
#define ACT_REG_NMODULES(x) ((x)(132, 128)) // 5 bit (0..31)
#define ACT_REG_NSTORAGE_CELLS(x) ((x)(148, 144)) // 5 bit
@@ -79,7 +78,6 @@ void data_collection_fsm(AXI_STREAM &eth_in,
volatile ap_uint<1> &in_run,
volatile ap_uint<1> &in_cancel,
volatile ap_uint<1> &out_idle,
uint32_t &counter,
ap_uint<32> mode,
ap_uint<32> one_over_energy,
ap_uint<32> nframes,

14
receiver/hls/host_writer.cpp
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@@ -18,8 +18,7 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
const ap_uint<32> &debug,
const ap_uint<64> &timestamp,
const ap_uint<64> &bunchid,
const ap_uint<32> &exptime,
const ap_uint<32> &data_collection_counter) {
const ap_uint<32> &exptime) {
#pragma HLS INLINE
ap_uint<1> all_packets_ok = packet_mask.and_reduce();
ap_uint<1> any_packets_received = packet_mask.or_reduce();
@@ -44,7 +43,7 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
m_axis_completion << exptime;
m_axis_completion << debug;
m_axis_completion << 0;
m_axis_completion << data_collection_counter;
m_axis_completion << 0;
m_axis_completion << packet_mask(127,96);
m_axis_completion << packet_mask( 95,64);
@@ -146,12 +145,11 @@ void host_writer(STREAM_512 &data_in,
data_in >> packet_in;
ap_uint<32> data_collection_mode = ACT_REG_MODE(packet_in.data);
ap_uint<1> mode_nonblocking = (data_collection_mode & MODE_NONBLOCKING_ON_WR) ? 1 : 0;
ap_uint<32> data_collection_counter = ACT_REG_COUNTER(packet_in.data);
ap_uint<8> internal_err_reg = 0;
err_reg = internal_err_reg;
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_counter);
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0);
idle = 0;
uint64_t total_counter = 0;
@@ -188,7 +186,7 @@ void host_writer(STREAM_512 &data_in,
write_completion(m_axis_completion, comp_handle, module,
comp_frame, comp_packet_mask, comp_packet_count,
comp_debug, comp_timestamp, comp_bunchid,
comp_exptime, data_collection_counter);
comp_exptime);
}
if (s_axis_work_request.empty() && mode_nonblocking) {
@@ -257,11 +255,11 @@ void host_writer(STREAM_512 &data_in,
write_completion(m_axis_completion, handle[m], m / 2, curr_frame[m],
packet_mask[m], packet_count[m],
debug[m], timestamp[m], jf_bunchid[m],
exptime[m], data_collection_counter);
exptime[m]);
}
data_in >> packet_in;
write_completion(m_axis_completion, HANDLE_END, 0, total_counter, 0, 0, 0, 0, 0, 0, data_collection_counter);
write_completion(m_axis_completion, HANDLE_END, 0, total_counter, 0, 0, 0, 0, 0, 0);
idle = 1;
}

7
receiver/host/AcquisitionDevice.cpp
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@@ -130,12 +130,8 @@ void AcquisitionDevice::StartAction(const DiffractionExperiment &experiment) {
auto c = work_completion_queue.GetBlocking();
while (c.type != Completion::Type::Start) {
if (logger)
logger->Info("Old message data collection ID {}", c.data_collection_counter );
c = work_completion_queue.GetBlocking();
c = work_completion_queue.GetBlocking();
}
if (logger)
logger->Info("Start message data collection ID {}", c.data_collection_counter );
StartSendingWorkRequests();
@@ -374,7 +370,6 @@ JFJochProtoBuf::FPGAStatus AcquisitionDevice::GetStatus() const {
ret.set_packets_sls(status.packets_sls);
ret.set_error_eth(status.udp_err_eth);
ret.set_error_packet_len(status.udp_err_len);
ret.set_data_collection_counter(status.data_collection_counter);
ret.set_host_writer_idle(full_status_register & (1<<4));
ret.set_frame_statistics_alignment_err(full_status_register & (1 << 24));

2
receiver/host/ActionConfig.h
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@@ -29,7 +29,7 @@ struct ActionStatus {
uint32_t git_sha1;
uint32_t action_type;
uint32_t release_level;
uint32_t data_collection_counter;
uint32_t reserved_3;
uint32_t reserved_1;
uint32_t max_modules;
uint32_t modules_internal_packet_generator;

1
receiver/host/Completion.cpp
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@@ -17,7 +17,6 @@ Completion parse_hw_completion(uint32_t tmp[16]) {
c.handle = tmp[0];
c.module = tmp[1] & 0xFF;
c.packet_count = (tmp[1] & (0xFFFF0000)) >> 16;
c.data_collection_counter = tmp[11];
uint64_t detector_frame_number = bit_concat(tmp[2], tmp[3]);
uint32_t parity = (std::bitset<32>(tmp[0]).count() + std::bitset<32>(tmp[1]).count()

1
receiver/host/Completion.h
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@@ -21,7 +21,6 @@ struct Completion {
uint32_t exptime;
uint32_t debug;
uint32_t handle;
uint32_t data_collection_counter;
uint16_t packet_count;
uint8_t module;
};

2
receiver/host/HLSSimulatedDevice.cpp
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@@ -272,7 +272,6 @@ void HLSSimulatedDevice::HLSMainThread() {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
cfg.mode,
cfg.one_over_energy,
cfg.nframes,
@@ -374,5 +373,4 @@ void HLSSimulatedDevice::HW_GetStatus(ActionStatus *status) const {
status->ctrl_reg = ap_uint<1>(host_writer_idle) ? (1 << 4) : 0;
status->modules_internal_packet_generator = 1;
status->max_modules = max_modules;
status->data_collection_counter = data_collection_counter;
}

1
receiver/host/HLSSimulatedDevice.h
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@@ -33,7 +33,6 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice {
ap_uint<1> run_data_collection;
ap_uint<1> cancel_data_collection;
volatile ap_uint<1> host_writer_idle;
uint32_t data_collection_counter;
uint64_t in_mem_location[LOAD_CALIBRATION_BRAM_SIZE];
static const uint64_t fpga_mac_addr = 0xCCAA11223344;

2
receiver/scripts/jfjoch.tcl
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@@ -427,8 +427,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net axis_work_completion_fifo_0_almost_full [get_bd_pins action_config_0/work_compl_fifo_full] [get_bd_pins axis_work_completion_fifo_0/almost_full]
connect_bd_net -net axis_work_request_fifo_0_almost_empty [get_bd_pins action_config_0/work_req_fifo_empty] [get_bd_pins axis_work_request_fifo_0/almost_empty]
connect_bd_net -net axis_work_request_fifo_0_almost_full [get_bd_pins action_config_0/work_req_fifo_full] [get_bd_pins axis_work_request_fifo_0/almost_full]
connect_bd_net -net data_collection_counter_0 [get_bd_pins data_collection_fsm_0/counter] [get_bd_pins action_config_0/data_collection_counter]
connect_bd_net -net data_collection_counter_valid_0 [get_bd_pins data_collection_fsm_0/counter_ap_vld] [get_bd_pins action_config_0/data_collection_counter_valid]
connect_bd_net -net data_collection_fsm_0_out_idle_V [get_bd_pins action_config_0/data_collection_idle] [get_bd_pins data_collection_fsm_0/out_idle]
connect_bd_net -net host_writer_0_err_reg_V [get_bd_pins action_config_0/host_writer_err] [get_bd_pins host_writer_0/err_reg]
connect_bd_net -net host_writer_0_err_reg_V_ap_vld [get_bd_pins action_config_0/host_writer_err_valid] [get_bd_pins host_writer_0/err_reg_ap_vld]

13
tests/FPGAIntegrationTest.cpp
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@@ -673,7 +673,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
ap_uint<1> run_data_collection = 0;
ap_uint<1> cancel_data_collection = 0;
ap_uint<1> idle_data_collection;
uint32_t data_collection_counter = 0;
uint32_t save_data_collection_counter;
act_reg.mode = MODE_CONV;
@@ -684,7 +683,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -693,7 +691,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
REQUIRE(idle_data_collection == 1);
REQUIRE(addr1.empty());
REQUIRE(raw1.empty());
save_data_collection_counter = data_collection_counter;
run_data_collection = 1;
@@ -703,7 +700,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -719,7 +715,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -738,7 +733,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -754,7 +748,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -772,7 +765,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -783,7 +775,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
REQUIRE(addr1.size() == 1);
REQUIRE(raw1.size() == 1);
REQUIRE(data_collection_counter == save_data_collection_counter + 1);
// state = INIT
cancel_data_collection = 1;
@@ -793,7 +784,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -811,7 +801,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -829,7 +818,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
run_data_collection,
cancel_data_collection,
idle_data_collection,
data_collection_counter,
act_reg.mode,
act_reg.one_over_energy,
act_reg.nframes,
@@ -851,7 +839,6 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") {
addr = addr1.read();
REQUIRE(addr_last_flag(addr));
REQUIRE(data_collection_counter == save_data_collection_counter + 1);
}
TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G0", "[FPGA][Full]") {